公开(公告)号：US20150003179A1

公开(公告)日：2015-01-01

申请号：US14086506

申请日：2013-11-21

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C11/4063

CPC classification number: G11C11/4063 ,  G11C11/40611 ,  G11C2211/4061

Abstract: A memory includes a plurality of word lines each coupled with at least one memory cell, an address storing unit that may store at least one target address corresponding to at least one of the word lines, and a control unit that may sequentially activate the plurality of word lines in response to a refresh command that is inputted at a set interval, and may activate the word line selected based on the target address whenever the refresh command is inputted a set number of times that is equal to or more than two times.

Abstract translation: 存储器包括多个与至少一个存储单元耦合的字线，地址存储单元，其可以存储与至少一个字线对应的至少一个目标地址;以及控制单元，其可以顺序地激活多个 响应于以设定间隔输入的刷新命令的字线，并且每当刷新命令被输入等于或大于两次的设定次数时，可以激活基于目标地址选择的字线。

公开(公告)号：US20140368238A1

公开(公告)日：2014-12-18

申请号：US14090858

申请日：2013-11-26

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G05F3/08

CPC classification number: G11C29/12005 ,  G01R31/31701 ,  G11C11/40

Abstract: A semiconductor device includes a normal code generation unit capable of generating a normal code, a test code output unit capable of storing a plurality of preliminary test codes to output a test code in response to a test control signal, and a reference voltage generation unit capable of generating a normal reference voltage in a normal operation mode and generating a test reference voltage in a test operation mode in response to the normal code and the test code.

Abstract translation: 半导体器件包括能够产生正常代码的正常代码生成单元，能够存储响应于测试控制信号输出测试代码的多个初步测试代码的测试代码输出单元，以及能够 在正常操作模式下产生正常参考电压，并响应于正常代码和测试代码在测试操作模式中产生测试参考电压。

公开(公告)号：US20160293267A1

公开(公告)日：2016-10-06

申请号：US15184762

申请日：2016-06-16

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C17/16 ,  G11C17/18

CPC classification number: G11C17/16 ,  G06F13/1636 ,  G11C11/40611 ,  G11C17/18 ,  G11C29/78 ,  G11C29/783

Abstract: A semiconductor memory device includes a command buffering unit suitable for receiving and buffering a command signal based on an enable control signal, a fuse array suitable for programming data based on the command signal, and an enable control unit suitable for generating the enable control signal, wherein an activation operation on the command buffering unit by the enable control signal is controlled during a programming operation period of the fuse array.

公开(公告)号：US20160180912A1

公开(公告)日：2016-06-23

申请号：US14709143

申请日：2015-05-11

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/409

CPC classification number: G11C11/40618 ,  G11C11/40611 ,  G11C11/4074 ,  G11C2211/4063

Abstract: A semiconductor device includes a first control block suitable for selectively blocking a refresh command signal based on a period signal having a predetermined activating pattern and a predetermined mode signal activated in a predetermined mode to generate a refresh group signal; and a second control block suitable for controlling a refresh operation based on the refresh group signal.

Abstract translation: 半导体器件包括：第一控制块，其适于基于具有预定激活模式的周期信号和以预定模式激活的预定模式信号选择性地阻塞刷新命令信号，以产生刷新组信号; 以及适于基于刷新组信号控制刷新操作的第二控制块。

公开(公告)号：US20150255140A1

公开(公告)日：2015-09-10

申请号：US14341451

申请日：2014-07-25

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/406

Abstract: A semiconductor memory device includes an address latch unit suitable for consecutively latching first refresh addresses, which correspond to successively-activated word lines, from consecutively received addresses for word lines to be activated in response to word line hit signals identifying the successively-activated word lines; an address comparison unit suitable for generating a comparison result signal by comparing the previously latched first address with the currently latched first address; a refresh control unit suitable for selecting a first refresh operation corresponding to the currently latched first address, and a second refresh operation corresponding to a second address in response to the comparison result signal, and a refresh command signal; and a refresh operation unit suitable for performing the first and second refresh operations on memory cells therein according to the selection of the refresh control unit.

Abstract translation: 一种半导体存储器件包括一个地址锁存单元，它适用于响应于识别连续激活的字线的字线命中信号，连续地锁存来自连续接收的连续接收的字线地址的第一刷新地址， ; 地址比较单元，适于通过将先前锁存的第一地址与当前锁存的第一地址进行比较来产生比较结果信号; 刷新控制单元，其适于选择与当前锁存的第一地址对应的第一刷新操作，以及响应于比较结果信号对应于第二地址的第二刷新操作和刷新命令信号; 以及适于根据刷新控制单元的选择对其中的存储单元执行第一和第二刷新操作的刷新操作单元。

公开(公告)号：US20150243375A1

公开(公告)日：2015-08-27

申请号：US14319966

申请日：2014-06-30

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C29/00 ,  G11C11/406 ,  G11C17/16

CPC classification number: G11C29/783 ,  G11C11/406 ,  G11C17/16

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells and a plurality of redundancy memory cells, a fuse array to be programmed with information of a defective memory cell among the memory cells of the memory cell array, and a control unit suitable for setting up a program operation section for programming the fuse array in response to an external command, wherein when the control unit sets up the program operation section, the control unit sets up a refresh operation section for refreshing the memory cell array, which is terminated before the program operation section ends without overlapping with the program operation section.

Abstract translation: 一种半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元和多个冗余存储单元，用存储单元阵列的存储单元中的有缺陷存储单元的信息编程的熔丝阵列，以及控制单元 适于设置用于响应于外部命令来编程熔丝阵列的程序操作部分，其中当控制单元设置程序操作部分时，控制单元设置用于刷新存储单元阵列的刷新操作部分 在程序操作部分结束之前终止而不与程序操作部分重叠。

公开(公告)号：US20150155030A1

公开(公告)日：2015-06-04

申请号：US14293694

申请日：2014-06-02

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G11C5/025 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C11/4087

Abstract: A semiconductor memory device includes a first bank, a second bank disposed separately from the first bank along a first direction, a third bank disposed separately from the first bank along a second direction substantially perpendicular to the first direction, a fourth bank disposed separately from the second bank along the second direction and from the third bank along the first direction, a first row control region, which is disposed between the first bank and the second bank, suitable for controlling a row decoding operation of the first bank and the second bank, a second row control region, which is disposed between the third bank and the fourth bank, suitable for controlling a row decoding operation of the third bank and the fourth bank, and a refresh control unit suitable for controlling a refresh operation of the first to fourth banks.

Abstract translation: 半导体存储器件包括第一组，沿第一方向与第一组分离设置的第二组，沿着基本上垂直于第一方向的第二方向与第一组分开设置的第三组，与第一组分开设置的第四组， 沿着第二方向的第二组和沿着第一方向的第三组，布置在第一组和第二组之间的第一行控制区，适于控制第一组和第二组的行解码操作， 布置在第三组和第四组之间的适于控制第三组和第四组的行解码操作的第二行控制区，以及适于控制第一至第四组的刷新操作的刷新控制单元 银行。

公开(公告)号：US20140177376A1

公开(公告)日：2014-06-26

申请号：US14085478

申请日：2013-11-20

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C8/08

CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4087 ,  G11C29/783

Abstract: A memory includes a first cell array including a plurality of first memory cells connected to a plurality of word lines, a bit line selection unit configured to select one or more bit lines among a plurality of bit lines based on repair information, a second cell array including a plurality of second memory cells connected to the plurality of word lines and the plurality of bit lines, wherein a group of the plurality of second memory cells connected to a corresponding word line stores the number of activations of the corresponding word line when the one or more connected bit lines are selected and an activation number update unit configured to update a value stored in the second memory cells, which are connected to the one or more selected bit lines and the activated word line among the plurality of word lines.

Abstract translation: 存储器包括：第一单元阵列，包括连接到多个字线的多个第一存储器单元;位线选择单元，被配置为基于修复信息来选择多个位线中的一个或多个位线;第二单元阵列 包括连接到所述多个字线和所述多个位线的多个第二存储器单元，其中连接到对应字线的所述多个第二存储器单元的一组存储当所述一行中相应字线的激活次数时 选择多个连接的位线，激活号码更新单元被配置为更新存储在第二存储器单元中的值，所述值连接到所述多个字线中的一个或多个所选择的位线和激活的字线。

公开(公告)号：US20140063994A1

公开(公告)日：2014-03-06

申请号：US13840715

申请日：2013-03-15

Applicant: SK HYNIX INC.

Inventor： Choung-Ki SONG

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C8/14 ,  G11C29/702 ,  G11C29/848

Abstract: A memory includes first to Nth word lines, first to Mth redundancy word lines configured to replace M number of word lines among the first to Nth word lines, and a control circuit configured to activate at least one adjacent word line adjacent to a Kth redundancy word line (1≦K≦M) in response to an active signal, in the case where a word line corresponding to an inputted address among the first to Nth word lines is replaced with the Kth redundancy word line among the first to Mth redundancy word lines in a first mode.

Abstract translation: 存储器包括第一至第N字线，第一至第M冗余字线，被配置为替换第一至第N字线中的M个字线，以及控制电路，被配置为激活与第K个冗余字相邻的至少一个相邻字线 在第一至第M冗余字线中替换与第一至第N字线中输入的地址对应的字线替换为第K冗余字线的情况下，响应于有效信号，线（1 @ K @ M） 在第一模式。

公开(公告)号：US20130346836A1

公开(公告)日：2013-12-26

申请号：US13716342

申请日：2012-12-17

Applicant: SK HYNIX INC.

Inventor： Choung-Ki SONG

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: A memory device includes a parity circuit configured to detect presence or absence of an error using a plurality of command signals and a plurality of address signals, a command shift circuit configured to shift the plurality of command signals by a preset delay value in synchronization with a control clock, a clock control circuit configured to deactivate the control clock when there is no valid command signal in command signals being shifted in the command shift circuit, and a decoder circuit configured to decode a plurality of command signals output from the command shift circuit.

Abstract translation: 存储装置包括：奇偶校验电路，被配置为使用多个命令信号和多个地址信号来检测是否存在错误，命令移位电路被配置为与多个命令信号同步地移位多个命令信号预定的延迟值 控制时钟，时钟控制电路，被配置为当在命令移位电路中的命令信号中没有有效的命令信号时停止控制时钟;以及解码器电路，被配置为解码从命令移位电路输出的多个命令信号。