公开(公告)号：US20180033485A1

公开(公告)日：2018-02-01

申请号：US15730388

申请日：2017-10-11

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C14/00 ,  G11C11/406 ,  G11C11/00 ,  G11C11/4072 ,  G11C5/14

CPC classification number: G11C14/0018 ,  G11C5/141 ,  G11C11/005 ,  G11C11/40615 ,  G11C11/4072 ,  G11C14/0009

Abstract: A memory module includes an emergency power supplier, a plurality of ranks each including one or more volatile memories a non-volatile memory, and a controller suitable for backing up data of the ranks into the non-volatile memory by using the emergency power supplier during a power failure, wherein the ranks are sequentially backed up, and while one rank is backed up among the ranks, the other ranks are controlled in a self-refresh mode.

公开(公告)号：US20160139203A1

公开(公告)日：2016-05-19

申请号：US14689944

申请日：2015-04-17

Applicant: SK hynix Inc.

Inventor： Jae-Seung LEE ,  Choung-Ki SONG

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31701 ,  G01R31/2601 ,  G01R31/2607 ,  G01R31/2851 ,  G01R31/31703

Abstract: A test setting circuit includes a first detection unit suitable for detecting whether a first code is sequentially inputted based on a first sequence, at each of first to Nth steps, where N is a natural number; a second detection unit suitable for sequentially receiving a second code through the first to Nth steps, and detecting whether the second code that is sequentially inputted through the first to Nth steps has a value corresponding to a second sequence; and a test setting unit suitable for setting a test mode when it is detected that the first code and the second code are inputted to satisfy the first sequence and the second sequence.

Abstract translation: 测试设置电路包括：第一检测单元，适于在第一至第N步骤中的每一个步骤中检测第一代码是否基于第一序列顺序地输入，其中N是自然数; 第二检测单元，适于通过第一至第N步骤顺序地接收第二代码，并且检测通过第一至第N步骤顺序输入的第二代码是否具有对应于第二序列的值; 以及测试设置单元，其适于在检测到第一代码和第二代码被输入时设置测试模式以满足第一序列和第二序列。

公开(公告)号：US20150371692A1

公开(公告)日：2015-12-24

申请号：US14489120

申请日：2014-09-17

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1087 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/2254

Abstract: A semiconductor device may include a first pad suitable for inputting a dock, a plurality of second pads suitable for inputting data through a plurality of first data paths, a third pad suitable for inputting a first strobe signal through a first strobe signal path, a data latch unit suitable for latching the data inputted through the first data paths in response to the first strobe signal inputted through the first strobe signal path, and a calibration control unit suitable for calibrating delay values of the plurality of first data paths and the first strobe signal path in a first calibration mode such that a plurality of first test signals passing through the respective first data paths and a second test signal passing through the first strobe path are in phase with the clock inputted from the first pad.

Abstract translation: 半导体器件可以包括适于输入基座的第一焊盘，适用于通过多个第一数据路径输入数据的多个第二焊盘，适于通过第一选通信号路径输入第一选通信号的第三焊盘，数据 锁存单元，用于响应于通过第一选通信号路径输入的第一选通信号，锁存通过第一数据路径输入的数据;以及校准控制单元，适于校准多个第一数据路径的延迟值和第一选通信号 路径，使得通过各个第一数据路径的多个第一测试信号和通过第一选通路径的第二测试信号与从第一焊盘输入的时钟同相。

公开(公告)号：US20150287461A1

公开(公告)日：2015-10-08

申请号：US14488976

申请日：2014-09-17

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C14/00 ,  G11C5/14 ,  G11C11/406

CPC classification number: G11C14/0018 ,  G11C5/141 ,  G11C11/005 ,  G11C11/40615 ,  G11C11/4072 ,  G11C14/0009

Abstract: A memory module includes an emergency power supplier, a plurality of ranks each including one or more volatile memories, a non-volatile memory, and a controller suitable for backing up data of the ranks into the non-volatile memory by using the emergency power supplier during a power failure, wherein the ranks are sequentially backed up, and while one rank is backed up among the ranks, the other ranks are controlled in a self-refresh mode.

Abstract translation: 存储器模块包括应急电源，多个等级，每个等级包括一个或多个易失性存储器，非易失性存储器，以及适于通过使用紧急电源供应器将行列数据备份到非易失性存储器中的控制器 在电源故障期间，其中排列顺序地备份，并且当在等级中备份一个等级时，其他队列被控制在自刷新模式中。

公开(公告)号：US20130336075A1

公开(公告)日：2013-12-19

申请号：US13716666

申请日：2012-12-17

Applicant: SK HYNIX INC.

Inventor： Choung-Ki SONG

IPC: G11C8/18 ,  G11C7/00

CPC classification number: G11C8/18 ,  G11C7/00 ,  G11C7/1045 ,  G11C11/4076 ,  G11C29/50012 ,  G11C2207/2272

Abstract: A memory device includes a decoder circuit configured to activate a setting signal and a write signal if a setting command is applied when a reference mode is set; a delay circuit configured to delay and to generate a delayed write signal; and a setting circuit configured to perform a setting operation in response to the delayed write signal and an input signal of a predetermined pad at the time of setting of the reference mode and to perform the setting operation in response to the setting signal when the reference mode is not set.

Abstract translation: 存储器件包括：解码器电路，被配置为当设置参考模式时施加设置命令时激活设置信号和写入信号; 延迟电路，被配置为延迟并产生延迟的写入信号; 以及设置电路，被配置为在设置参考模式时响应于延迟的写入信号和预定焊盘的输入信号执行设置操作，并且当参考模式被设置时，响应于设置信号执行设置操作 没有设置。

公开(公告)号：US20130335115A1

公开(公告)日：2013-12-19

申请号：US13717498

申请日：2012-12-17

Applicant: SK HYNIX INC.

Inventor： Choung-Ki SONG

IPC: H03K19/00 ,  G05F3/00

CPC classification number: H03K19/0005 ,  G05F3/00

Abstract: A integrated circuit includes a clock control signal generation circuit configured to generate a clock control signal using transition of a control signal, a clock control unit configured to activate a control clock in an activated period of the clock control signal, and to deactivate the control clock in a deactivated period of the clock control signal, and a control circuit configured to operate in response to the control signal and in synchronization with the control clock.

Abstract translation: 集成电路包括：时钟控制信号生成电路，被配置为使用控制信号的转换来生成时钟控制信号;时钟控制单元，被配置为在时钟控制信号的激活时段中激活控制时钟;以及停止控制时钟 在时钟控制信号的去激活时段中，以及控制电路，被配置为响应于控制信号并与控制时钟同步地操作。

公开(公告)号：US20160336058A1

公开(公告)日：2016-11-17

申请号：US14863092

申请日：2015-09-23

Applicant: SK Hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C7/109

Abstract: A semiconductor device includes: a command decoding unit suitable for decoding external command signals to generate an internal command signal; and a pulse control unit suitable for controlling a pulse width of the internal command signal.

Abstract translation: 半导体器件包括：命令解码单元，适于解码外部命令信号以产生内部命令信号; 以及适于控制内部命令信号的脉冲宽度的脉冲控制单元。

公开(公告)号：US20150331769A1

公开(公告)日：2015-11-19

申请号：US14489064

申请日：2014-09-17

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G06F11/20 ,  G06F3/06 ,  G11C5/14

CPC classification number: G06F11/1441 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/2015 ,  G06F11/2094 ,  G11C5/04 ,  G11C5/14 ,  G11C5/141

Abstract: A memory module includes an emergency power supply block, a volatile memory, a nonvolatile memory, and a control block configured to control data of the volatile memory to be backed up in the nonvolatile memory, by using a power supplied from the emergency power supply block, upon a power failure, and control the data of the volatile memory to be recovered, by using data backed up in the nonvolatile memory, upon a power recovery, wherein the control block controls the data of the volatile memory not to be backed up while controlling the data of the volatile memory to be recovered, even upon the power failure.

Abstract translation: 存储器模块包括应急电源块，易失性存储器，非易失性存储器和控制块，其被配置为通过使用从应急电源块提供的电力来控制要备份在非易失性存储器中的易失性存储器的数据 在电源故障时，通过使用在非易失性存储器中备份的数据来控制要恢复的易失性存储器的数据，其中控制块控制易失性存储器的数据不被备份，同时 即使在电源故障时也控制要恢复的易失性存储器的数据。

公开(公告)号：US20150043292A1

公开(公告)日：2015-02-12

申请号：US14109582

申请日：2013-12-17

Applicant: SK hynix Inc.

Inventor： Yo-Sep LEE ,  Choung-Ki SONG

IPC: G11C29/08

CPC classification number: G11C29/50012 ,  G11C29/025 ,  G11C29/08 ,  G11C2029/1202 ,  G11C2029/5002

Abstract: A memory may include a plurality of word lines to which one or more memory cells are connected, and a control unit suitable for activating and precharging a first word line that is selected based on an address of a high-activated word line during a target refresh operation while sequentially activating and precharging the plurality of word lines in a refresh operation, wherein the control unit is suitable for writing a test data to one or more first memory cells connected to the first word line during the target refresh operation in a test mode, wherein the high-activated word line is a word line activated over a reference number or a reference frequency, among the plurality of word lines.

Abstract translation: 存储器可以包括连接一个或多个存储器单元的多个字线，以及适于在目标刷新期间基于高激活字线的地址来选择的第一字线的激活和预充电的控制单元 在刷新操作中顺序地激活和预充电多个字线的操作，其中所述控制单元适合于在测试模式期间的目标刷新操作期间将测试数据写入连接到第一字线的一个或多个第一存储器单元， 其中所述高激活字线是在所述多个字线中的参考数字或参考频率上激活的字线。

公开(公告)号：US20150016201A1

公开(公告)日：2015-01-15

申请号：US14090945

申请日：2013-11-26

Applicant: SK hynix Inc.

Inventor： Hye-Young LEE ,  Kie-Bong KU ,  Choung-Ki SONG ,  Sung-Hwa OK ,  Se-Jin YOO

IPC: G11C7/10

CPC classification number: G11C7/1006 ,  G11C7/1012 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/105

Abstract: A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode.

Abstract translation: 半导体器件包括耦合到彼此电绝缘的第一和第二数据线的第一和第二组组。 该半导体器件包括适于在特定模式中向第二数据线提供预定数据的寄存器单元，适于外部输出加载到第二数据线上的预定数据的数据传输和输出单元，并同时将预定数据传送到第一数据线 数据线，以及适于在特定模式中外加输出加载到第一数据线上的预定数据的数据输出单元。