公开(公告)号：US20150188526A1

公开(公告)日：2015-07-02

申请号：US14243154

申请日：2014-04-02

Applicant: SK hynix Inc.

Inventor： Hoon CHOI ,  Seung Geun BAEK

IPC: H03K5/13

CPC classification number: H03K5/13 ,  H03K2005/00026

Abstract: A delay circuit of a semiconductor apparatus includes a control signal generation block configured to output a control signal having an analog voltage level in response to an input signal, and an input/output block configured to delay the input signal by a delay amount based on the analog voltage level of the control signal, and output a resultant signal.

Abstract translation: 半导体装置的延迟电路包括：控制信号生成块，其被配置为响应于输入信号输出具有模拟电压电平的控制信号;以及输入/输出块，被配置为基于所述输入信号延迟所述输入信号延迟量 控制信号的模拟电压电平，并输出合成信号。

公开(公告)号：US20130329507A1

公开(公告)日：2013-12-12

申请号：US13710630

申请日：2012-12-11

Applicant: SK HYNIX INC.

Inventor： Hoon CHOI ,  Jin Hee CHO

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C7/1066

Abstract: An output enable signal generation circuit includes an output enable reset signal generation unit configured to enable an output enable reset signal in response to an external clock signal, a DLL locking signal, and a reset signal, an output enable reset signal delay unit configured to delay the output enable reset signal and output the delayed output enable reset signal, a counter unit configured to output the count of the external clock signal as a value in response to the output enable reset signal and the delayed output enable reset signal, a read command delay unit configured to delay a read command and output the delayed read command, and an output enable signal output unit configured to shift the delayed read command in synchronization with a DLL clock signal and output an output enable signal, according to control of CL and the count value.

Abstract translation: 输出使能信号生成电路包括：输出使能复位信号生成部，被配置为响应于外部时钟信号，DLL锁定信号和复位信号使能输出使能复位信号;输出使能复位信号延迟部，被配置为延迟 输出使能复位信号并输出​​延迟的输出使能复位信号;计数器单元，被配置为响应于输出使能复位信号和延迟的输出使能复位信号输出外部时钟信号的计数值，读出指令延迟 被配置为延迟读取命令并输出延迟读取命令的单元，以及输出使能信号输出单元，被配置为与DLL时钟信号同步地移位延迟读取命令，并且根据CL的控制和计数输出输出使能信号 值。

公开(公告)号：US20150213845A1

公开(公告)日：2015-07-30

申请号：US14278895

申请日：2014-05-15

Applicant: SK hynix Inc.

Inventor： Hoon CHOI ,  Seung Geun BAEK

IPC: G11C5/14 ,  G11C7/22

CPC classification number: G11C5/147 ,  G06F13/1668 ,  G11C7/1063 ,  Y02D10/14

Abstract: A system includes a memory device, a controller, and a power supply. The controller stores a write data in the memory device, and generates a voltage control signal by comparing a read data outputted from the memory device with the write data. The power supply controls a level of a power supply voltage supplied to the memory device in response to the voltage control signal.

Abstract translation: 系统包括存储器件，控制器和电源。 控制器将写入数据存储在存储器件中，并且通过将从存储器件输出的读取数据与写入数据进行比较来产生电压控制信号。 电源控制响应于电压控制信号而提供给存储器件的电源电压的电平。

公开(公告)号：US20140062552A1

公开(公告)日：2014-03-06

申请号：US13710748

申请日：2012-12-11

Applicant: SK HYNIX INC.

Inventor： Hoon CHOI

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/0812

Abstract: A delay-locked loop (DLL) circuit having improved phase correction performance includes a variable delay unit configured to generate a DLL clock signal by delaying an input clock signal by a varied delay time in response to a delay control signal at timing corresponding to an update cycle signal, a delay model configured to generate a feedback clock signal by delaying the DLL clock signal for a predetermined delay time, a phase detection unit configured to output a result of the detection of the phase of the feedback clock signal based on a reference clock signal as the delay control signal, and an update cycle control unit configured to determine whether a cycle has been shifted or not in response to an external clock signal and the delay control signal and shift a cycle where the update cycle signal is generated based on a result of the determination.

Abstract translation: 具有改进的相位校正性能的延迟锁定环路（DLL）电路包括可变延迟单元，该可变延迟单元被配置为通过响应于对应于更新的定时的延迟控制信号，延迟输入时钟信号一个变化的延迟时间来产生DLL时钟信号 周期信号，延迟模型，被配置为通过将DLL时钟信号延迟预定的延迟时间来产生反馈时钟信号;相位检测单元，被配置为基于参考时钟输出反馈时钟信号的相位的检测结果 信号作为延迟控制信号，以及更新周期控制单元，被配置为响应于外部时钟信号和延迟控制信号确定周期是否被移位，并且基于a产生更新周期信号的周期 决定的结果。