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    Low-latency time-to-digital converter with reduced quantization step
    1.
    发明授权
    Low-latency time-to-digital converter with reduced quantization step 有权

    公开(公告)号：US11923856B2

    公开(公告)日：2024-03-05

    申请号：US17713901

    申请日：2022-04-05

    Applicant: XILINX, INC.

    Inventor： Bob W. Verbruggen ,  Christophe Erdmann

    IPC: H03K5/00 ,  H03K5/135 ,  H03K5/14 ,  H03K5/15 ,  H03K19/0948 ,  H03M1/82

    CPC classification number: H03K5/14 ,  H03K5/135 ,  H03K5/15066 ,  H03K19/0948 ,  H03M1/82 ,  H03K2005/00026

    Abstract: Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.

    Delay structure for a memory interface
    3.
    发明授权
    Delay structure for a memory interface 有权
    存储器接口的延迟结构

    公开(公告)号：US09520864B2

    公开(公告)日：2016-12-13

    申请号：US14298742

    申请日：2014-06-06

    Applicant: QUALCOMM Incorporated

    Inventor： Jan Christian Diffenderfer ,  Yuehchun Claire Cheng

    IPC: H03K5/13 ,  G11C7/10 ,  H03K5/135 ,  H03K5/00

    CPC classification number: H03K5/13 ,  G11C7/1072 ,  H03K5/131 ,  H03K5/135 ,  H03K2005/00026 ,  H03K2005/00247 ,  H03K2005/00286

    Abstract: Systems and methods for delaying a signal are described herein. In one embodiment, a method for delaying a signal comprises receiving a first signal edge, and, in response to receiving the first signal edge, counting a number of oscillations of an oscillator. The method also comprises outputting a second signal edge if the number of oscillations reaches a predetermined number. The second signal edge represents a delayed version of the first signal edge.

    Abstract translation: 本文描述了用于延迟信号的系统和方法。 在一个实施例中，一种用于延迟信号的方法包括接收第一信号边缘，并且响应于接收到第一信号边沿，对振荡器的振荡次数进行计数。 该方法还包括如果振荡次数达到预定数量则输出第二信号沿。 第二信号边缘表示第一信号边沿的延迟版本。

    Wave clocking
    6.
    发明授权
    Wave clocking 有权
    波时钟

    公开(公告)号：US08810300B2

    公开(公告)日：2014-08-19

    申请号：US13331796

    申请日：2011-12-20

    Applicant: Tim Sippel

    Inventor： Tim Sippel

    IPC: G06F1/04

    CPC classification number: H03L7/0802 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F12/14 ,  G06F21/44 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/0375 ,  H03K5/133 ,  H03K19/01 ,  H03K2005/00019 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/097 ,  H03L7/0997 ,  H01L2924/00

    Abstract: Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.

    Abstract translation: 实施例提供了用于基于IC电源电压来动态地调节集成电路（IC）的时钟频率的系统和方法。 通过这样做，时钟频率不再受最坏情况电压电平的约束，并且可以支持更高的有效时钟频率，从而提高了IC性能。 实施例包括波时钟系统，其使用被配置为基本上匹配IC的相应逻辑路径的延迟的多个延迟链。 随着逻辑路径的延迟随着电源电压和温度的变化而变化，与逻辑路径匹配的延迟链经历基本类似的改变，并用于调节IC的时钟频率。

    Low noise wide range voltage-controlled oscillator with transistor feedback
    7.
    发明授权
    Low noise wide range voltage-controlled oscillator with transistor feedback 有权
    具有晶体管反馈的低噪声宽范围压控振荡器

    公开(公告)号：US08686799B2

    公开(公告)日：2014-04-01

    申请号：US11968082

    申请日：2007-12-31

    Applicant: Stanley J. Goldman

    Inventor： Stanley J. Goldman

    IPC: H03K3/03

    CPC classification number: H03L7/0995 ,  H03K3/0315 ,  H03K2005/00026 ,  H03K2005/00195 ,  H03L7/183

    Abstract: An integrated circuit, a voltage controlled oscillator (VCO) and a phase-locked loop (PLL). In one embodiment, the VCO includes: (1) a voltage tune line configured to receive a tuning voltage for the VCO and (2) an odd number of ring-coupled delay elements. Each of the delay elements includes: (2A) an inverter having a power supply line being coupled to the voltage tune line and (2B) a feedback path having a gain-attenuating transistor with a gate thereof being coupled to the voltage tune line.

    Abstract translation: 集成电路，压控振荡器（VCO）和锁相环（PLL）。 在一个实施例中，VCO包括：（1）被配置为接收VCO的调谐电压的电压调谐线和（2）奇数个环耦合延迟元件。 每个延迟元件包括：（2A）具有耦合到电压调制线的电源线的反相器和（2B）具有增益衰减晶体管的反馈路径，其中栅极耦合到电压调谐线。

    Pre-Heating For Reduced Subthreshold Leakage
    8.
    发明申请
    Pre-Heating For Reduced Subthreshold Leakage 有权
    预热减少亚阈值泄漏

    公开(公告)号：US20140028344A1

    公开(公告)日：2014-01-30

    申请号：US14041505

    申请日：2013-09-30

    Applicant: Broadcom Corporation

    Inventor： Paul Penzes ,  Mark Fullerton

    IPC: H03K19/01

    CPC classification number: H03L7/0802 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F12/14 ,  G06F21/44 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/0375 ,  H03K5/133 ,  H03K19/01 ,  H03K2005/00019 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/097 ,  H03L7/0997 ,  H01L2924/00

    Abstract: Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high, threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given minimum temperature at which the IC is designed or guaranteed) to properly function at are provided.

    Abstract translation: 某些半导体工艺提供在单个IC中使用具有不同阈值电压的多种不同类型的晶体管。 可以看出，在这些半导体工艺中的某些中，高阈值晶体管可以运行的速度随着温度的降低而降低。 因此，实现高阈值晶体管的IC的总体处理速度通常受IC设计（或保证）以适当地起作用的最低温度的限制。 通过“预热”IC（或实现高阈值晶体管的IC的至少部分）来克服这种缺陷的系统和方法的实施例，使得IC可以以高于 在设计或保证集成电路的给定最低温度下，可以提供正确的功能）。

    Delay control circuit and method
    9.
    发明授权
    Delay control circuit and method 有权
    延时控制电路及方法

    公开(公告)号：US08633750B2

    公开(公告)日：2014-01-21

    申请号：US11575306

    申请日：2005-09-05

    Applicant: Bernardus M. Kup

    Inventor： Bernardus M. Kup

    IPC: H03L7/00

    CPC classification number: H04L7/02 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  H03K5/135 ,  H03K2005/00026 ,  H03L7/0812 ,  H04L7/0008 ,  H04L7/0338

    Abstract: The present invention relates to a delay control circuit and a method of controlling delay of an output signal generating based on an input signal, wherein a plurality of delayed replicas of a reference signal are generated with dedicated time delays with respect to the reference signal and are sampled at a predetermined timing defined by the input signal. One of the delayed replicas is selected based on the output of the sampling means, and the output signal is generated based on the selected replica. Thereby, a predetermined phase relationship can be generated even in cases where no strict phase relation is given between data and reference signal.

    Abstract translation: 本发明涉及一种延迟控制电路和一种控制基于输入信号产生的输出信号的延迟的方法，其中基准信号的多个延迟复制产生相对于参考信号的专用时间延迟，并且分别是 在由输入信号定义的预定定时进行采样。 基于采样装置的输出选择延迟复制中的一个，并且基于所选择的副本生成输出信号。 因此，即使在数据和参考信号之间没有严格的相位关系的情况下也可以产生预定的相位关系。

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