公开(公告)号：US20230298631A1

公开(公告)日：2023-09-21

申请号：US17884963

申请日：2022-08-10

Applicant: SK hynix Inc.

Inventor： Jae Hyung PARK ,  Seung Geun BAEK ,  Dong Uk LEE

IPC: G11C5/02 ,  H01L25/065 ,  H01L25/18 ,  G11C8/10

CPC classification number: G11C5/02 ,  H01L25/0657 ,  H01L25/18 ,  G11C8/10 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A stacked semiconductor device includes at least one upper chip including a plurality of channels each including first and second pseudo-channels; and a plurality of transfer control circuits respectively corresponding to the channels and each configured to output channel commands according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel of the channels, and transmit first and second data words between the corresponding channel and a lower chip according to the channel commands.

公开(公告)号：US20170366169A1

公开(公告)日：2017-12-21

申请号：US15697076

申请日：2017-09-06

Applicant: SK hynix Inc.

Inventor： Seung Geun BAEK ,  Jae Il KIM

IPC: H03H11/28

CPC classification number: H03H11/28 ,  H03K19/0005

Abstract: An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.

公开(公告)号：US20170062050A1

公开(公告)日：2017-03-02

申请号：US15049795

申请日：2016-02-22

Applicant: SK hynix Inc.

Inventor： Seung Geun BAEK ,  Jae Il KIM

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C7/04 ,  G11C7/1057 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03K19/0005

Abstract: A semiconductor device may include a ZQ calibration circuit, a reference code setting circuit, a variable information generating circuit, and an internal circuit. The ZQ calibration circuit may perform a ZQ calibration operation in response to a ZQ calibration enable signal to generate a ZQ calibration code. The reference code generating circuit may output a predetermined code value as a reference code. The variable information generating circuit may compare the ZQ calibration code to the reference code to generate variable information. The internal circuit may determine operation timings based on a difference between the ZQ calibration code and the reference code.

Abstract translation: 半导体器件可以包括ZQ校准电路，参考码设置电路，可变信息产生电路和内部电路。 ZQ校准电路可以响应于ZQ校准使能信号执行ZQ校准操作以产生ZQ校准码。 参考码产生电路可以输出预定码值作为参考码。 可变信息生成电路可以将ZQ校准代码与参考代码进行比较，以产生可变信息。 内部电路可以基于ZQ校准代码和参考代码之间的差异来确定操作定时。

公开(公告)号：US20150188526A1

公开(公告)日：2015-07-02

申请号：US14243154

申请日：2014-04-02

Applicant: SK hynix Inc.

Inventor： Hoon CHOI ,  Seung Geun BAEK

IPC: H03K5/13

CPC classification number: H03K5/13 ,  H03K2005/00026

Abstract: A delay circuit of a semiconductor apparatus includes a control signal generation block configured to output a control signal having an analog voltage level in response to an input signal, and an input/output block configured to delay the input signal by a delay amount based on the analog voltage level of the control signal, and output a resultant signal.

Abstract translation: 半导体装置的延迟电路包括：控制信号生成块，其被配置为响应于输入信号输出具有模拟电压电平的控制信号;以及输入/输出块，被配置为基于所述输入信号延迟所述输入信号延迟量 控制信号的模拟电压电平，并输出合成信号。

公开(公告)号：US20240339438A1

公开(公告)日：2024-10-10

申请号：US18747448

申请日：2024-06-19

Applicant: SK hynix Inc.

Inventor： Jae Hyung PARK ,  Seung Geun BAEK ,  Dong Uk LEE

IPC: H01L25/065 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096 ,  H10B80/00

CPC classification number: H01L25/0657 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  H10B80/00 ,  H01L2225/06513

Abstract: A stacked semiconductor device includes at least one upper chip including first and second channels, each including first and second pseudo-channels; and first and second transfer control circuits respectively corresponding to the first and second channels, each configured to select one of the first and second pseudo-channels according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel, and transfer a data word between the selected pseudo-channel and a lower chip, wherein the first transfer control circuit transfers the data word in a first order in units of bytes, and the second transfer control circuit transfers the data word in a second order in units of bytes, opposite to the first order.

公开(公告)号：US20180165024A1

公开(公告)日：2018-06-14

申请号：US15605207

申请日：2017-05-25

Applicant: SK hynix Inc.

Inventor： Seung Geun BAEK ,  Jin Hee CHO

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/06 ,  G06F2212/1032

Abstract: A semiconductor device includes a group control circuit configured to generate a specified address and a control code in response to a row address and an active command, a comparison control signal generation circuit configured to generate a comparison control signal in response to the active command and a set code, and a target address generation circuit configured to output the specified address as a target address in response to the control code and the comparison control signal.

公开(公告)号：US20170053715A1

公开(公告)日：2017-02-23

申请号：US14933203

申请日：2015-11-05

Applicant: SK hynix Inc.

Inventor： Jae Il KIM ,  Seung Geun BAEK ,  Don Hyun CHOI

IPC: G11C29/00 ,  G11C11/408 ,  G11C11/406 ,  G11C11/4096

CPC classification number: G11C29/76 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4096

Abstract: Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time. The semiconductor device may include a repair detection unit configured to determine whether an inputted address is a repair address and output a repair detection signal. The semiconductor device may include a refresh control unit configured to simultaneously activate two or more word lines in response to a refresh command signal and sequentially activate the two or more word lines according to the repair detection signal.

Abstract translation: 各种实施例通常涉及半导体器件和用于半导体器件的器件，更具体地，涉及与数据保留时间的裕度有关的技术。 半导体器件可以包括修复检测单元，其被配置为确定输入的地址是否是修复地址并输出修复检测信号。 半导体器件可以包括刷新控制单元，其被配置为响应于刷新命令信号同时激活两个或更多个字线，并且根据修复检测信号顺序激活两个或更多个字线。

公开(公告)号：US20160252572A1

公开(公告)日：2016-09-01

申请号：US14724430

申请日：2015-05-28

Applicant: SK hynix Inc.

Inventor： Seung Geun BAEK

IPC: G01R31/315 ,  G01R1/067 ,  G01R31/302

CPC classification number: G01R31/315 ,  G01R31/2884 ,  G01R31/3025

Abstract: A semiconductor integrated circuit device including a variable frequency type probe test pad and a semiconductor system are disclosed. The semiconductor integrated circuit device includes a plurality of probe test pads formed on a semiconductor substrate and configured to induce non-contact electrical coupling with a probe card, and a frequency control unit electrically coupled to each of the plurality of probe test pads, and configured to vary a frequency of each of the plurality of probe test pads.

Abstract translation: 公开了一种包括可变频率型探针测试垫和半导体系统的半导体集成电路器件。 半导体集成电路器件包括多个探针测试焊盘，形成在半导体衬底上，并被配置为引入与探针卡的非接触电耦合;以及频率控制单元，电耦合到多个探针测试焊盘中的每一个，并配置 以改变多个探针测试垫中的每一个的频率。

公开(公告)号：US20240339134A1

公开(公告)日：2024-10-10

申请号：US18746052

申请日：2024-06-18

Applicant: SK hynix Inc.

Inventor： Jae Hyung PARK ,  Seung Geun BAEK ,  Dong Uk LEE

IPC: G11C5/02 ,  G11C8/10 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C5/02 ,  G11C8/10 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A stacked semiconductor device includes at least one upper chip including a plurality of channels each including first and second pseudo-channels; and a plurality of transfer control circuits respectively corresponding to the channels and each configured to output channel commands according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel of the channels, and transmit first and second data words between the corresponding channel and a lower chip according to the channel commands.

公开(公告)号：US20170134006A1

公开(公告)日：2017-05-11

申请号：US15409057

申请日：2017-01-18

Applicant: SK hynix Inc.

Inventor： Seung Geun BAEK ,  Jae Il KIM

IPC: H03H11/28

CPC classification number: H03H11/28 ,  H03K19/0005

Abstract: An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.