公开(公告)号：US20220083223A1

公开(公告)日：2022-03-17

申请号：US17204117

申请日：2021-03-17

Applicant: SK hynix Inc.

Inventor： Hoon CHOI ,  Beom Ju SHIN

IPC: G06F3/06

Abstract: A storage device includes a memory device and a memory controller. The memory device includes a first plane and a second plane, each including data blocks configured to store user data, one or more replacement blocks configured to replace one or more bad blocks, and system blocks configured to store system information. The memory controller is configured to replace, when a bad block is detected in the first plane after all the one or more replacement blocks in the first plane are used to replace previously detected bad blocks, the detected bad block with a target system block selected among the system blocks in the first plane.

公开(公告)号：US20150102838A1

公开(公告)日：2015-04-16

申请号：US14106828

申请日：2013-12-15

Applicant: SK hynix Inc.

Inventor： Seung-Geun BAEK ,  Hoon CHOI

IPC: H03K19/003

CPC classification number: H03K19/003 ,  G11C7/1084 ,  G11C7/1093 ,  H03K3/0375 ,  H03K5/08 ,  H03K5/135 ,  H03K5/1536 ,  H04L7/0008

Abstract: A semiconductor device includes a signal detection unit suitable for detecting a state of an input signal and generating a detection signal based on a detected result, and a signal transmission unit suitable for selectively transmitting the input signal in response to the detection signal, wherein the signal detection unit includes a state signal generation unit suitable for detecting a level shifting time of the input signal, and generating a state signal at a detected level shifting time, and a state determination unit suitable for comparing a voltage level of the input signal with a voltage level of a reference voltage in response to the state signal, and outputting the detection signal.

Abstract translation: 一种半导体器件，包括适于检测输入信号的状态并基于检测结果生成检测信号的信号检测单元，以及响应于检测信号选择性地发送输入信号的信号传输单元，其中信号 检测单元包括适于检测输入信号的电平移位时间的状态信号生成单元，并且以检测到的电平移位时间生成状态信号;以及状态判定单元，其适于将输入信号的电压电平与电压 响应于状态信号的参考电压电平，并输出检测信号。

公开(公告)号：US20220108734A1

公开(公告)日：2022-04-07

申请号：US17220320

申请日：2021-04-01

Applicant: SK hynix Inc.

Inventor： Jung Shik JANG ,  Hoon CHOI ,  Dong Hun LEE ,  Yun Sik CHOI

IPC: G11C7/12 ,  G11C7/10

Abstract: The present technology relates to a page buffer and a semiconductor memory device including the same. The page buffer includes a bit line selector configured to connect a bit line of a memory cell array to a sensing node, a precharger configured to precharge a potential of the sensing node to a first level, and a latch component configured to sense data by detecting a time at which the potential of the sensing node is decreased from the first level to a second level.

公开(公告)号：US20180090224A1

公开(公告)日：2018-03-29

申请号：US15416268

申请日：2017-01-26

Applicant: SK hynix Inc.

Inventor： Hoon CHOI

IPC: G11C29/12 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C29/1201 ,  G11C7/08 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/22 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/40 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/4402

Abstract: Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to control the memory cell array, the peripheral circuit including a first region disposed under the memory cell array and a second region; and a fall sensing unit configured to sense whether a failure has occurred in the first or the second regions.

公开(公告)号：US20150002203A1

公开(公告)日：2015-01-01

申请号：US14489618

申请日：2014-09-18

Applicant: SK hynix Inc.

Inventor： Hoon CHOI

IPC: H03K5/13 ,  H03K5/22

CPC classification number: H03K5/13 ,  H03K5/22 ,  H03K21/406

Abstract: An integrated circuit includes a clock control unit configured to selectively output an external clock or a delayed clock acquired by delaying the external clock as an input clock in response to a divided clock generated by dividing the external clock, when a test mode is entered; and an internal circuit operating in response to the input clock.

Abstract translation: 集成电路包括：时钟控制单元，被配置为当输入测试模式时，响应于通过划分外部时钟产生的分频时钟，选择性地输出外部时钟或延迟时钟，所述延迟时钟通过将外部时钟延迟为输入时钟; 以及响应于输入时钟而工作的内部电路。

公开(公告)号：US20150187401A1

公开(公告)日：2015-07-02

申请号：US14244153

申请日：2014-04-03

Applicant: SK HYNIX INC.

Inventor： Hoon CHOI

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/225 ,  G11C8/18 ,  G11C11/4076 ,  G11C29/023

Abstract: A semiconductor memory apparatus may include a clock buffer configured to receive an external clock signal, buffer the external clock signal in response to an activation control signal, and the clock buffer configured to output an internal clock signal in response to an activation control signal. The semiconductor memory apparatus may also include a delay-locked loop block configured to receive the internal clock signal outputted from the clock buffer and compare phases of the internal clock signal and a feedback clock signal, and responsively generate a delay-locked clock signal. The semiconductor memory apparatus may also include an operation control block configured to responsively generate the activation control signal which is received by the clock buffer in accordance with a result of comparing the phases of the internal clock signal and the feedback clock signal, in response to receiving a read signal.

Abstract translation: 半导体存储装置可以包括被配置为接收外部时钟信号的时钟缓冲器，响应于激活控制信号缓冲外部时钟信号，并且时钟缓冲器被配置为响应于激活控制信号而输出内部时钟信号。 半导体存储装置还可以包括延迟锁定环路块，被配置为接收从时钟缓冲器输出的内部时钟信号，并且比较内部时钟信号和反馈时钟信号的相位，并且响应地产生延迟锁定时钟信号。 半导体存储装置还可以包括操作控制块，其被配置成响应于接收到的响应地响应于根据比较内部时钟信号和反馈时钟信号的相位的结果响应地产生由时钟缓冲器接收的激活控制信号 读信号。

公开(公告)号：US20150153794A1

公开(公告)日：2015-06-04

申请号：US14243663

申请日：2014-04-02

Applicant: SK hynix Inc.

Inventor： Hoon CHOI ,  Sang Don LEE ,  Yeon Uk KIM ,  Seok Joon KANG

IPC: G06F1/26 ,  G06F1/30

CPC classification number: G06F1/26 ,  G11C5/14 ,  G11C16/30

Abstract: A system includes a power supply, a memory controller and a memory device. The memory controller is configured to receive power from the power supply, generate a memory power supply voltage for use by the memory device based on the power received from the power supply and provide the memory power supply voltage to the memory device.

Abstract translation: 系统包括电源，存储器控制器和存储器件。 存储器控制器被配置为从电源接收电力，基于从电源接收的功率生成存储器设备使用的存储器电源电压，并将存储器电源电压提供给存储器件。

公开(公告)号：US20130321046A1

公开(公告)日：2013-12-05

申请号：US13711566

申请日：2012-12-11

Applicant: SK HYNIX INC.

Inventor： Min Su PARK ,  Hoon CHOI

IPC: H03L5/00

CPC classification number: H03L5/00 ,  H03L7/0816

Abstract: A semiconductor device having a power tracking circuit configured for activating a power tracking signal for a period corresponding to a period during which an external voltage retains a level lower than a level of a low power mode reference voltage if the external voltage retains the level lower than the level of the low power mode reference voltage for at least a preselected time.

Abstract translation: 一种具有功率跟踪电路的半导体器件，其配置用于在外部电压保持低于低功率模式参考电压的电平的电平保持低于低功率模式参考电压的电平的周期期间激活功率跟踪信号。 至少预选时间的低功率模式参考电压的电平。

公开(公告)号：US20160013796A1

公开(公告)日：2016-01-14

申请号：US14798854

申请日：2015-07-14

Applicant: SK hynix Inc.

Inventor： Hoon CHOI

IPC: H03L7/08 ,  H03L7/095 ,  H03L7/081

CPC classification number: H03L7/0802 ,  H03L7/0818 ,  H03L7/095

Abstract: A semiconductor device may include a delay line including a first group of unit delay cells and a second group of unit delay cells. The first group of unit delay cells and the second group of unit delay cells may be configured for delaying a phase of a clock by a unit cycle of a reference frequency. The reference frequency may serve as a reference for distinguishing between a first frequency and a second frequency. The semiconductor device may include a reservoir capacitor located adjacent to one or more of the unit delay cells of the first group. Only the first group of the unit delay cells may be used to delay the phase of the clock.

Abstract translation: 半导体器件可以包括延迟线，延迟线包括第一组单位延迟单元和第二组单位延迟单元。 第一组单元延迟单元和第二组单位延迟单元可以被配置为将时钟的相位延迟参考频率的单位周期。 参考频率可以用作区分第一频率和第二频率的参考。 半导体器件可以包括与第一组的单个延迟单元中的一个或多个相邻的储存器电容器。 可以仅使用第一组单位延迟单元来延迟时钟的相位。

公开(公告)号：US20150226786A1

公开(公告)日：2015-08-13

申请号：US14453422

申请日：2014-08-06

Applicant: SK hynix Inc.

Inventor： Seung-Geun BAEK ,  Hoon CHOI

IPC: G01R31/26

CPC classification number: G11C29/021 ,  G11C29/028 ,  G11C2029/0401

Abstract: A semiconductor system includes a semiconductor device suitable for generating measuring data, and a controller suitable for comparing the measuring data with a given expected value and controlling a voltage level, which is supplied to the semiconductor device, based on the comparison result.

Abstract translation: 半导体系统包括适于产生测量数据的半导体器件，以及适于根据比较结果将测量数据与给定期望值进行比较并控制提供给半导体器件的电压电平的控制器。