公开(公告)号：US20210065826A1

公开(公告)日：2021-03-04

申请号：US16827358

申请日：2020-03-23

Applicant: SK hynix Inc.

Inventor： Jiman HONG

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G06F3/06

Abstract: A memory device may include a memory cell array, a program and verify circuit, a verify table storage, and a program fail detector. The memory cell array may include memory cells. The program and verify circuit may perform a program operation of programming the memory cells to a corresponding target state of a plurality of states, and generate verification data including cell count values that respectively correspond to one or more states among the plurality of states. The verify table storage may store, for each program pulse count, reference data including reference cell count values that respectively correspond to the plurality of states. The program fail detector may detect whether the program operation has failed based on a result of a comparison between the verification data and the reference data corresponding to a current program pulse count, and generate program fail information indicating that the program operation has failed.

公开(公告)号：US20200350023A1

公开(公告)日：2020-11-05

申请号：US16673646

申请日：2019-11-04

Applicant: SK hynix Inc.

Inventor： Jiman HONG

IPC: G11C16/26 ,  G11C16/04 ,  G06F3/06 ,  G06F11/10

Abstract: The memory controller may include a command generator generating and outputting first and second read commands to a memory device so that respective first and second read operations are performed using a first read voltage, a calculator receiving first and second read data in response to the read commands, comparing the first and second read data each other, and calculating a number of first inverted cells and a number of second inverted cells based on a result of the comparing, each of the first inverted cells having a bit value that inverted from a first bit value to a second bit value, and each of the second inverted cells having a bit value that inverted from the second bit value to the first bit value, and a read voltage determiner changing the first read voltage depending on the number of first inverted cells and the number of second inverted cells.

公开(公告)号：US20200065018A1

公开(公告)日：2020-02-27

申请号：US16355001

申请日：2019-03-15

Applicant: SK hynix Inc.

Inventor： Jiman HONG

IPC: G06F3/06 ,  G06F12/10

Abstract: A memory controller controls operations of a memory device. The memory controller includes a group read count storage and a data distribution controller. The group read count storage divides logical block addresses corresponding to data stored in the memory device into a plurality of logical block address groups and stores respective read count values of the data corresponding to the logical block addresses according to the logical block address groups. The data distribution controller controls the memory device to distribute and store data corresponding to a target logical block address group selected among the plurality of logical block address groups in a plurality of memory blocks based on the read count values stored according to the logical block address groups.

公开(公告)号：US20190332472A1

公开(公告)日：2019-10-31

申请号：US16196471

申请日：2018-11-20

Applicant: SK hynix Inc.

Inventor： Jiman HONG

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  G11C16/10 ,  G11C11/56 ,  G11C16/26 ,  G11C7/10

Abstract: An operating method of memory system may include: reading target data stored in a target memory page, using a plurality of read voltages, respectively; sequentially storing read data corresponding to the target data in a plurality of latches including a first latch and a second latch, respectively; performing a first error correction code (ECC) decoding operation on first read data stored in the first latch; and performing a second ECC decoding operation on second read data stored in the second latch, when the first ECC decoding operation fails.

公开(公告)号：US20180374552A1

公开(公告)日：2018-12-27

申请号：US15881243

申请日：2018-01-26

Applicant: SK hynix Inc.

Inventor： Jiman HONG

IPC: G11C16/34 ,  G11C16/26 ,  G06F11/10 ,  G11C29/52 ,  G11C16/04

Abstract: A memory system comprising: a nonvolatile memory device including a plurality of pages, and suitable for performing one among a first program operation of performing program and verify operations according to an incremental step pulse programming (ISPP) scheme and a second program operation of first performing a verify operation and then performing program and verify operations according to the ISPP scheme when the program operation is to be performed to each of the plurality of pages; and a controller suitable for controlling the nonvolatile memory device to perform the second program operation when a target page meets an operation condition of a reprogram, and to perform the first program operation when the target page does not meet the operation condition of the reprogram.