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公开(公告)号：US20250054552A1
公开(公告)日：2025-02-13
申请号：US18807792
申请日：2024-08-16
Applicant: STMicroelectronics International N.V.
Inventor： Vikas RANA , Neha DALAL
Abstract: The present disclosure is directed to an integrated circuit that includes a non-volatile memory (NVM). The integrated circuit includes a bias generator that produces stable wordline and bitline voltages for a reliable read operation of the NVM. This disclosure is directed to low voltage memory operations of memory read, erase verify, and program verify. The present disclosure is directed to non-volatile memory circuits that can also operate at low supply voltages in digital voltage supply range.
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12.发明申请公开(公告)号：US20230008272A1
公开(公告)日：2023-01-12
申请号：US17837377
申请日：2022-06-10
Applicant: STMicroelectronics International N.V.
Inventor： Vikas RANA , Vivek TYAGI
Abstract: An integrated circuit die includes memory sectors, each memory sector including a memory array. The die includes a voltage regulator with a first transistor driven by an output voltage to thereby generate a gate voltage, the output voltage being generated based upon a difference between a constant current and a leakage current. A selection circuit selectively couples the gate voltage to a selected one of the plurality of memory sectors. A leakage detector circuit drives a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current, increases the variable current in response to the copy voltage being greater than the gate voltage, and asserts a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array.
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公开(公告)号：US20210375333A1
公开(公告)日：2021-12-02
申请号：US17321344
申请日：2021-05-14
Applicant: STMicroelectronics International N.V.
Inventor： Vikas RANA , Arpit VIJAYVERGIA
IPC: G11C7/06
Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
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公开(公告)号：US20210050778A1
公开(公告)日：2021-02-18
申请号：US16911967
申请日：2020-06-25
Applicant: STMicroelectronics International N.V.
Inventor： Vikas RANA
IPC: H02M3/07
Abstract: A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.
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15.发明申请公开(公告)号：US20200235660A1
公开(公告)日：2020-07-23
申请号：US16742248
申请日：2020-01-14
Applicant: STMicroelectronics International N.V.
Inventor： Vikas RANA , Shivam KALLA
IPC: H02M3/07
Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a control signal. A diode has an anode coupled to the first node and a cathode coupled to a second node. A current mirror arrangement sources a first current to the second node and sinks a second current from a third node. A comparator causes the control signal to direct the charge pump circuit to generate the charge pump output signal as having a voltage that ramps upwardly in magnitude (but negative in sign) if the voltage at the second node is greater than the voltage at the third node, and causes the control signal to direct the charge pump circuit to cease the ramping of the voltage of the charge pump output signal if the voltage at the second node is at least equal to the voltage at the third node.
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Patent Agency Ranking
公开(公告)号：US20220172751A1
公开(公告)日：2022-06-02
申请号：US17534136
申请日：2021-11-23
Applicant: STMicroelectronics International N.V.
Inventor： Shivam KALLA , Vikas RANA
Abstract: An integrated circuit includes a non-volatile memory, a charge pump that generates high voltages for programming operations of the non-volatile memory array, and a charge pump regulator that controls a slew rate of the charge pump. The charge pump regulator generates a sense current indicative of the slew rate and adjusts a frequency of a clock signal provided to the charge pump based on the sense current.
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公开(公告)号：US20220165317A1
公开(公告)日：2022-05-26
申请号：US17542203
申请日：2021-12-03
Inventor： Vivek TYAGI , Vikas RANA , Chantal AURICCHIO , Laura CAPECCHI
IPC: G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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公开(公告)号：US20220158552A1
公开(公告)日：2022-05-19
申请号：US17494244
申请日：2021-10-05
Applicant: STMicroelectronics International N.V.
Inventor： Vikas RANA
Abstract: The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.
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19.发明申请公开(公告)号：US20220068400A1
公开(公告)日：2022-03-03
申请号：US17006510
申请日：2020-08-28
Inventor： Marco PASOTTI , Dario LIVORNESI , Roberto BREGOLI , Vikas RANA , Abhishek MITTAL
Abstract: An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.
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公开(公告)号：US20210074340A1
公开(公告)日：2021-03-11
申请号：US17010704
申请日：2020-09-02
Inventor： Vivek TYAGI , Vikas RANA , Chantal AURICCHIO , Laura CAPECCHI
IPC: G11C7/12 , G11C7/06 , G11C7/22 , G11C11/4091 , G11C11/4094
Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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