公开(公告)号：US20220068400A1

公开(公告)日：2022-03-03

申请号：US17006510

申请日：2020-08-28

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Marco PASOTTI ,  Dario LIVORNESI ,  Roberto BREGOLI ,  Vikas RANA ,  Abhishek MITTAL

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/34

Abstract: An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.

公开(公告)号：US20240404569A1

公开(公告)日：2024-12-05

申请号：US18675916

申请日：2024-05-28

Applicant: STMicroelectronics International N.V.

Inventor： Marcella CARISSIMI ,  Marco PASOTTI ,  Riccardo ZURLA

IPC: G11C7/16 ,  G06F7/544 ,  G11C11/54 ,  G11C13/00

Abstract: An in-memory computation (IMC) device is configured to receive input data and provide intermediate output data. A word line activation circuit receives input data and provides corresponding word line activation signals. A memory array includes memory cells in a matrix arrangement coupled to bit lines and to word lines. Each bit line is traversed by a respective bit line current depending on the memory cells connected to the bit line. Selectors each coupled to a respective part of the bit lines are configured to select one of the respective bit lines. A digital detector for each selector is electrically connected, through the respective selector, with the respective bit line selected. The digital detectors sample the respective bit line currents and, in response to the bit line currents, provide the respective intermediate output data.

公开(公告)号：US20240404594A1

公开(公告)日：2024-12-05

申请号：US18731676

申请日：2024-06-03

Applicant: STMicroelectronics International N.V.

Inventor： Marcella CARISSIMI ,  Marco PASOTTI ,  Riccardo ZURLA

IPC: G11C13/00 ,  G06F7/544

Abstract: An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.

公开(公告)号：US20240404568A1

公开(公告)日：2024-12-05

申请号：US18731557

申请日：2024-06-03

Applicant: STMicroelectronics International N.V.

Inventor： Riccardo ZURLA ,  Marco PASOTTI

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

Abstract: An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.

公开(公告)号：US20250080118A1

公开(公告)日：2025-03-06

申请号：US18241813

申请日：2023-09-01

Applicant: STMicroelectronics International N.V.

Inventor： Marco PASOTTI ,  Riccardo ZURLA ,  Marcella CARISSIMI ,  Riccardo VIGNALI ,  Alessandro CABRINI

IPC: H03K21/02

Abstract: An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

公开(公告)号：US20250078922A1

公开(公告)日：2025-03-06

申请号：US18241812

申请日：2023-09-01

Applicant: STMicroelectronics International N.V.

Inventor： Marcella CARISSIMI ,  Marco PASOTTI ,  Riccardo ZURLA

IPC: G11C13/00 ,  G06F7/523

Abstract: A memory array includes memory cells arranged in a matrix with cell rows coupled to word lines and cell columns coupled to output bit lines. A control circuit maps a first group of memory cells to a first in-memory compute operation producing computation output signals on first output bit lines from a first matrix vector multiplication of a first input vector with a first group of computation weights stored in the first group of memory cells and maps a second group of memory cells to a second in-memory compute operation producing computation output signals on second output bit lines, different from the first output bit lines, from a second matrix vector multiplication of a second input vector, different from the first input vector, with a second group of computation weights stored in the second group of memory cells. The first and second in-memory compute operations are substantially simultaneously executed.

公开(公告)号：US20250046371A1

公开(公告)日：2025-02-06

申请号：US18790867

申请日：2024-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Marco PASOTTI ,  Riccardo VIGNALI ,  Alessandro CABRINI ,  Riccardo ZURLA

IPC: G11C13/00

Abstract: An in-memory computation device receives an input signal and provides an output signal. The device includes a memory array with memory cells coupled to word lines that receive word line activation signals indicative of the input signal and coupled to bit lines that generate bit line currents; and a digital detector for sampling the bit line current and, in response, providing the output signal. A digital detector includes: a control stage that compares the bit line current with at least one reference current and generates corresponding control signals; a selection stage that generates a total selection current based on the first bit line current and on the control signals; an integration stage that samples the total selection current; and a charge counter stage that generates the output signal on the basis of a sampled first total selection current and the control signals.

公开(公告)号：US20230238055A1

公开(公告)日：2023-07-27

申请号：US17582675

申请日：2022-01-24

Applicant: STMicroelectronics S.r.l. ,  Alma Mater Studiorum - Universita' Di Bologna

Inventor： Marco PASOTTI ,  Marcella CARISSIMI ,  Antonio GNUDI ,  Eleonora FRANCHI SCARSELLI ,  Alessio ANTOLINI ,  Andrea LICO

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4076 ,  G06F7/544

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4076 ,  G06F7/5443

Abstract: A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.

公开(公告)号：US20150212880A1

公开(公告)日：2015-07-30

申请号：US14597824

申请日：2015-01-15

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Marcella CARISSIMI ,  Marco PASOTTI

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C7/18 ,  G11C11/5642 ,  G11C16/0441 ,  G11C16/26 ,  G11C16/28 ,  G11C2211/4013

Abstract: A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word.

Abstract translation: 差分存储器件包括具有直接存储单元和补充存储单元的存储单元。 相应的方法包括接收读取与所选码字相关联的所选数据字的请求，读取表示所选码字的差分版本的差分码字，根据纠错码验证差分码字，设置所选择的码字 数据字根据差分代码字响应积极的验证。 该方法还包括读取表示所选码字的单端版本的至少一个单端码字，根据纠错码验证单端码字，并根据单频码字单位设置所选择的数据字， 响应于对差分代码字的否定验证和对单端代码字的肯定验证，结束代码字。

公开(公告)号：US20140036564A1

公开(公告)日：2014-02-06

申请号：US13954908

申请日：2013-07-30

Applicant: STMicroelectronics PVT LTD ,  STMicroelectronics S.r.l.

Inventor： Fabio DE SANTIS ,  Marco PASOTTI ,  Abhishek LAL

IPC: G11C5/02

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C7/18 ,  G11C8/12 ,  G11C16/00 ,  G11C16/08 ,  G11C16/24

Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.

Abstract translation: 非易失性存储器件的实施例包括：存储器阵列，其具有布置在至少一个逻辑行中的多个非易失性逻辑存储器单元，所述逻辑行包括共享公共控制线的第一行和第二行; 和多个位线。 每个逻辑存储器单元具有用于存储逻辑值的直接存储单元和用于存储第二逻辑值的互补存储器单元，该第二逻辑值与对应的直接存储器单元中的第一逻辑值互补。 每个逻辑存储单元的直接存储单元和互补存储单元被耦合到相应的单独的位线，并且被放置在相应的逻辑行的第二行中的第一行而另一个中。