公开(公告)号：US10553499B2

公开(公告)日：2020-02-04

申请号：US15993922

申请日：2018-05-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Frédéric Chairat ,  Noémie Blanc ,  Emmanuel Blot ,  Philippe Roux ,  Gerald Theret

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/84 ,  H01L27/092 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/306 ,  H01L29/06 ,  H01L27/12 ,  H01L27/11521

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.

公开(公告)号：US11424342B2

公开(公告)日：2022-08-23

申请号：US16939767

申请日：2020-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Franck Julien

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/027 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/78

Abstract: In fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs), the implanting of lightly doped drain regions is performed before forming gate regions with a physical gate length that is associated with a reference channel length. The step of implanting lightly doped drain regions includes forming an implantation mask defining the lightly doped drain regions and an effective channel length of each MOSFET. The forming of the implantation mask is configured to define an effective channel length of at least one MOSFET that is different from the respective reference channel length.

公开(公告)号：US11121042B2

公开(公告)日：2021-09-14

申请号：US16739592

申请日：2020-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Frédéric Chairat ,  Noémie Blanc ,  Emmanuel Blot ,  Philippe Roux ,  Gerald Theret

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/84 ,  H01L27/092 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/306 ,  H01L29/06 ,  H01L27/12 ,  H01L21/311 ,  H01L27/11521

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.

公开(公告)号：US10930757B2

公开(公告)日：2021-02-23

申请号：US16228032

申请日：2018-12-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Arnaud Regnier ,  Dann Morillon ,  Franck Julien ,  Marjorie Hesse

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

Abstract: A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.

公开(公告)号：US20200258773A1

公开(公告)日：2020-08-13

申请号：US16860392

申请日：2020-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3105 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/02 ,  H01L21/311

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.

公开(公告)号：US20200152523A1

公开(公告)日：2020-05-14

申请号：US16739592

申请日：2020-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Frédéric Chairat ,  Noémie Blanc ,  Emmanuel Blot ,  Philippe Roux ,  Gerald Theret

IPC: H01L21/8238 ,  H01L27/12 ,  H01L29/06 ,  H01L21/306 ,  H01L21/762 ,  H01L21/3115 ,  H01L27/092 ,  H01L21/84 ,  H01L21/02 ,  H01L21/311

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.

公开(公告)号：US10332808B2

公开(公告)日：2019-06-25

申请号：US15897003

申请日：2018-02-14

Applicant: Commissariat a l'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Stephan Niel ,  Emmanuel Richard ,  Olivier Weber

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/12 ,  H01L27/092

Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.

公开(公告)号：US20180358270A1

公开(公告)日：2018-12-13

申请号：US15993922

申请日：2018-05-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Frédéric Chairat ,  Noémie Blanc ,  Emmanuel Blot ,  Philippe Roux ,  Gerald Theret

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/306 ,  H01L29/06

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.