公开(公告)号：US11522057B2

公开(公告)日：2022-12-06

申请号：US17100559

申请日：2020-11-20

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Franck Julien ,  Stephan Niel ,  Leo Gave

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/66

Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.

公开(公告)号：US11640921B2

公开(公告)日：2023-05-02

申请号：US17068112

申请日：2020-10-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Abderrezak Marzaki

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L25/16 ,  H01L25/18

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

公开(公告)号：US20190006229A1

公开(公告)日：2019-01-03

申请号：US15992481

申请日：2018-05-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.

公开(公告)号：US11183505B2

公开(公告)日：2021-11-23

申请号：US16939603

申请日：2020-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Abderrezak Marzaki

IPC: H01L27/11531 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L21/311 ,  H01L27/11521

Abstract: A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.

公开(公告)号：US10672644B2

公开(公告)日：2020-06-02

申请号：US15992481

申请日：2018-05-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/092 ,  H01L21/3105 ,  H01L21/28 ,  H01L29/66

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.

公开(公告)号：US20180269115A1

公开(公告)日：2018-09-20

申请号：US15897003

申请日：2018-02-14

Applicant: Commissariat a l'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Stephan Niel ,  Emmanuel Richard ,  Olivier Weber

IPC: H01L21/84 ,  H01L29/51 ,  H01L27/12 ,  H01L21/28

CPC classification number: H01L21/84 ,  H01L21/28008 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/51

Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.

公开(公告)号：US12198973B2

公开(公告)日：2025-01-14

申请号：US18127751

申请日：2023-03-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Abderrezak Marzaki

IPC: H01L25/16 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L25/18

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

公开(公告)号：US12125899B2

公开(公告)日：2024-10-22

申请号：US17180197

申请日：2021-02-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Arnaud Regnier ,  Dann Morillon ,  Franck Julien ,  Marjorie Hesse

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66568 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654

Abstract: A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.

公开(公告)号：US11817484B2

公开(公告)日：2023-11-14

申请号：US17935754

申请日：2022-09-27

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Franck Julien ,  Stephan Niel ,  Leo Gave

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L29/518 ,  H01L29/6634

Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.

公开(公告)号：US10777552B2

公开(公告)日：2020-09-15

申请号：US16046683

申请日：2018-07-26

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Franck Julien

IPC: H01L29/00 ,  H01L27/088 ,  H01L21/8236 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423

Abstract: The disclosure relates to a method of simultaneous fabrication of an MOS transistor of SOI type, and of first and second transistors on bulk substrate, comprising: a) providing a semiconductor layer on an insulating layer covering a semiconductor substrate; b) forming a mask comprising, above the location of the second transistor, a central opening which is less wide than the second transistor to be formed; c) plumb with the opening, entirely etching the semiconductor layer and insulating layer, hence resulting in remaining portions of the insulating layer at the location of the second transistor; d) growing the semiconductor by epitaxy as far as the upper level of the semiconductor layer; e) forming isolating trenches; and f) forming the gate insulators of the transistors, the gate insulator of the second transistor comprising at least one part of the said remaining portions of the insulating layer.