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    Device for generating an adjustable bandgap reference voltage with large power supply rejection rate
    12.
    发明授权
    Device for generating an adjustable bandgap reference voltage with large power supply rejection rate 有权

    公开(公告)号：US09298202B2

    公开(公告)日：2016-03-29

    申请号：US14616481

    申请日：2015-02-06

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Jimmy Fort ,  Thierry Soude

    IPC: G05F1/625 ,  G05F3/30

    CPC classification number: G05F1/625 ,  G05F3/30

    Abstract: An adjustable bandgap reference voltage includes a first circuit for generating IPTAT, a second circuit for generating ICTAT, and an output module configured to generate the reference voltage. The first circuit includes a first amplifier connected to terminals of a core for equalizing voltages across the terminals, where the first amplifier has a first stage that is biased by the current inversely proportional to absolute temperature and is arranged according to a folded setup with first PMOS transistors arranged according to a common-gate setup. The first circuit also includes a feedback stage with an input connected to the first amplifier output. The feedback stage output is connected to the first stage input and to a terminal of the core. The second circuit includes a follower amplifier connected to a terminal of the core and separated from the first amplifier and the output module is connected to the feedback stage.

    Regulator with Low Dropout Voltage and Improved Stability
    14.
    发明申请
    Regulator with Low Dropout Voltage and Improved Stability 有权
    具有低压差和稳定性的稳压器

    公开(公告)号：US20130241649A1

    公开(公告)日：2013-09-19

    申请号：US13827044

    申请日：2013-03-14

    Applicant: STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Jimmy Fort ,  Thierry Soude

    IPC: H03F3/45

    CPC classification number: G05F1/575 ,  H03F3/45179

    Abstract: The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node.

    Abstract translation: 具有低压降电压的调节器包括误差放大器，该误差放大器包括差分输入晶体管对和连接到所述差分对的输出的折叠共源共栅结构的电路，连接到误差放大器的输出节点的输出级，以及 米勒补偿电容连接在共源共栅电路的输出侧（XP）的输出级与共源共栅节点之间; 误差放大器还包括在所述共源共栅节点和连接在所述共源共栅节点和所述输出节点之间的共源共栅电路的共源共栅晶体管的栅极之间的反馈回路中的至少一个反相放大器模块。

    Method and device for generating an adjustable bandgap reference voltage
    18.
    发明授权
    Method and device for generating an adjustable bandgap reference voltage 有权

    公开(公告)号：US09804631B2

    公开(公告)日：2017-10-31

    申请号：US15243556

    申请日：2016-08-22

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Jimmy Fort ,  Thierry Soude

    IPC: G05F3/26 ,  G05F3/30 ,  G05F1/46

    CPC classification number: G05F3/267 ,  G05F1/468 ,  G05F3/30

    Abstract: A circuit includes a first PMOS transistor that includes a first PMOS source coupled to a first input node, a first PMOS gate, and a first PMOS drain. A second PMOS transistor includes a second PMOS source coupled to a second input node, a second PMOS gate, and a second PMOS drain coupled to the second PMOS gate. A first resistor coupled between the first PMOS source and a ground node. A first diode element coupled between the first resistor and the ground node and a second diode element coupled between the second PMOS source and the ground node. A third PMOS transistor includes a third PMOS gate, a third PMOS source coupled to a supply node, and a third PMOS drain coupled to the first input node. A fourth PMOS transistor includes a fourth PMOS gate coupled to the third PMOS gate, a fourth PMOS source coupled to the supply node, and a fourth PMOS drain coupled to the second input node.

    Method and Device for Generating an Adjustable Bandgap Reference Voltage
    19.
    发明申请
    Method and Device for Generating an Adjustable Bandgap Reference Voltage 审中-公开
    用于产生可调带隙参考电压的方法和装置

    公开(公告)号：US20160357213A1

    公开(公告)日：2016-12-08

    申请号：US15243556

    申请日：2016-08-22

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Jimmy Fort ,  Thierry Soude

    IPC: G05F3/26

    CPC classification number: G05F3/267 ,  G05F1/468 ,  G05F3/30

    Abstract: A circuit includes a first PMOS transistor that includes a first PMOS source coupled to a first input node, a first PMOS gate, and a first PMOS drain. A second PMOS transistor includes a second PMOS source coupled to a second input node, a second PMOS gate, and a second PMOS drain coupled to the second PMOS gate. A first resistor coupled between the first PMOS source and a ground node. A first diode element coupled between the first resistor and the ground node and a second diode element coupled between the second PMOS source and the ground node. A third PMOS transistor includes a third PMOS gate, a third PMOS source coupled to a supply node, and a third PMOS drain coupled to the first input node. A fourth PMOS transistor includes a fourth PMOS gate coupled to the third PMOS gate, a fourth PMOS source coupled to the supply node, and a fourth PMOS drain coupled to the second input node.

    Abstract translation: 电路包括第一PMOS晶体管，其包括耦合到第一输入节点的第一PMOS源极，第一PMOS栅极和第一PMOS漏极。 第二PMOS晶体管包括耦合到第二输入节点的第二PMOS源极，第二PMOS栅极和耦合到第二PMOS栅极的第二PMOS漏极。 耦合在第一PMOS源极和接地节点之间的第一电阻器。 耦合在第一电阻器和接地节点之间的第一二极管元件和耦合在第二PMOS源极和接地节点之间的第二二极管元件。 第三PMOS晶体管包括第三PMOS栅极，耦合到电源节点的第三PMOS源极和耦合到第一输入节点的第三PMOS漏极。 第四PMOS晶体管包括耦合到第三PMOS栅极的第四PMOS栅极，耦合到电源节点的第四PMOS源极和耦合到第二输入节点的第四PMOS漏极。

    Regulator with Low Dropout Voltage and Improved Stability
    20.
    发明申请
    Regulator with Low Dropout Voltage and Improved Stability 审中-公开

    公开(公告)号：US20160062377A1

    公开(公告)日：2016-03-03

    申请号：US14937671

    申请日：2015-11-10

    Applicant: STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Jimmy Fort ,  Thierry Soude

    IPC: G05F1/575

    CPC classification number: G05F1/575 ,  H03F3/45179

    Abstract: The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node.

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