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公开(公告)号:US20220321124A1
公开(公告)日:2022-10-06
申请号:US17846362
申请日:2022-06-22
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Nicolas Borrel , Jimmy Fort , Mathieu Lisart
IPC: H03K19/003 , H03F3/45 , H03K19/00 , H03K19/17736 , H03L7/097
Abstract: A physically unclonable function device includes a set of diode-connected MOS transistors having a random distribution of respective threshold voltages. A first circuit is configured to impose, on each first transistor, a fixed respective gate voltage regardless of the value of a current flowing in this first transistor. A second circuit is configured to impose, on each second transistor, a fixed respective gate voltage regardless of the value of a current flowing in this second transistor. A current mirror stage is coupled between the first circuit and the second circuit and is configured to deliver the reference current from a sum of the currents flowing in the first transistors. A comparator is configured to deliver a signal whose level depends on a comparison between a first current obtained from a reference current based on the first transistors and a second current of the second transistors.
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公开(公告)号:US11069628B2
公开(公告)日:2021-07-20
申请号:US16292958
申请日:2019-03-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Abderrezak Marzaki , Mathieu Lisart
Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.
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公开(公告)号:US10950559B2
公开(公告)日:2021-03-16
申请号:US16436747
申请日:2019-06-10
Inventor: Mathieu Lisart , Bruce Rae
Abstract: An electronic integrated circuit chip includes a semiconductor substrate with a front side and a back side. A first reflective shield is positioned adjacent the front side of the semiconductor substrate and a second reflective shield is positioned adjacent the back side of the semiconductor substrate. Photons are emitted by a photon source to pass through the semiconductor substrate and bounce off the first and second reflective shields to reach a photon detector at the front side of the semiconductor substrate. The detected photons are processed in order to determine whether to issue an alert indicating the existence of an attack on the electronic integrated circuit chip.
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公开(公告)号:US20180145040A1
公开(公告)日:2018-05-24
申请号:US15596767
申请日:2017-05-16
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Christian Rivero , Pascal Fornara , Guilhem Bouton , Mathieu Lisart
IPC: H01L23/00 , H01L27/088 , H01L23/528 , H01L21/311
CPC classification number: H01L23/573 , H01L21/31111 , H01L21/768 , H01L21/76802 , H01L21/76816 , H01L21/823475 , H01L23/522 , H01L23/5226 , H01L23/5283 , H01L23/585 , H01L24/03 , H01L24/06 , H01L27/088
Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
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公开(公告)号:US20170141913A1
公开(公告)日:2017-05-18
申请号:US15138573
申请日:2016-04-26
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Mathieu Lisart , Benoit Durand , Massimo Cervetto , Christophe Laurencin
CPC classification number: H04L9/004 , G06F21/556 , G06F21/74 , G06F21/85 , G06F2221/2123 , G06F2221/2127
Abstract: A circuit includes a first processing unit and a second identical processing unit. A first communication bus passes encrypted data between one of a plurality of functions and one or both of the first and second processing units. A selection circuit determines whether the encrypted bus is coupled to the first processing unit, the second processing unit, or both of the first and second processing units.
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公开(公告)号:US11818883B2
公开(公告)日:2023-11-14
申请号:US17540029
申请日:2021-12-01
Inventor: Abderrezak Marzaki , Mathieu Lisart , Benoit Froment
CPC classification number: H10B20/367 , G11C16/0466 , H01L23/57
Abstract: The present description concerns a ROM including at least one first rewritable memory cell.
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公开(公告)号:US11804842B2
公开(公告)日:2023-10-31
申请号:US17846362
申请日:2022-06-22
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Nicolas Borrel , Jimmy Fort , Mathieu Lisart
IPC: H03K5/22 , H03K19/003 , H03F3/45 , H03K19/00 , H03K19/17736 , H03L7/097 , H04L9/32
CPC classification number: H03K19/00384 , H03F3/45273 , H03F3/45488 , H03K19/0027 , H03K19/17744 , H03L7/097 , H04L9/3278 , H04L2209/12
Abstract: A physically unclonable function device includes a set of diode-connected MOS transistors having a random distribution of respective threshold voltages. A first circuit is configured to impose, on each first transistor, a fixed respective gate voltage regardless of the value of a current flowing in this first transistor. A second circuit is configured to impose, on each second transistor, a fixed respective gate voltage regardless of the value of a current flowing in this second transistor. A current mirror stage is coupled between the first circuit and the second circuit and is configured to deliver the reference current from a sum of the currents flowing in the first transistors. A comparator is configured to deliver a signal whose level depends on a comparison between a first current obtained from a reference current based on the first transistors and a second current of the second transistors.
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公开(公告)号:US11531049B2
公开(公告)日:2022-12-20
申请号:US17322140
申请日:2021-05-17
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Clement Champeix , Mathieu Dumont , Nicolas Borrel , Mathieu Lisart
Abstract: An embodiment integrated circuit includes a first electromagnetic pulse detection device that comprises a first loop antenna formed in an interconnection structure of the integrated circuit, a first end of the first antenna being connected to a first node of application of a power supply potential and a second end of the antenna being coupled to a second node of application of the power supply potential, and a first circuit connected to the second end of the first antenna and configured to output a first signal representative of a comparison of a first current in the first antenna with a first threshold.
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公开(公告)号:US11387197B2
公开(公告)日:2022-07-12
申请号:US17166156
申请日:2021-02-03
Inventor: Mathieu Lisart , Bruce Rae
IPC: H01L23/00
Abstract: An electronic integrated circuit chip includes a semiconductor substrate with a front side and a back side. A first reflective shield is positioned adjacent the front side of the semiconductor substrate and a second reflective shield is positioned adjacent the back side of the semiconductor substrate. Photons are emitted by a photon source to pass through the semiconductor substrate and bounce off the first and second reflective shields to reach a photon detector at the front side of the semiconductor substrate. The detected photons are processed in order to determine whether to issue an alert indicating the existence of an attack on the electronic integrated circuit chip.
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公开(公告)号:US10861802B2
公开(公告)日:2020-12-08
申请号:US16208253
申请日:2018-12-03
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Christian Rivero , Pascal Fornara , Guilhem Bouton , Mathieu Lisart
IPC: H01L21/311 , H01L23/00 , H01L23/58 , H01L21/8234 , H01L23/528 , H01L27/088 , H01L23/522 , H01L21/768
Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
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