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    PROTECTION OF A MODULAR CALCULATION
    13.
    发明申请
    PROTECTION OF A MODULAR CALCULATION 审中-公开

    公开(公告)号：US20180060566A1

    公开(公告)日：2018-03-01

    申请号：US15442303

    申请日：2017-02-24

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Ibrahima Diop ,  Pierre-Yvan Liardet ,  Yanis Linge

    IPC: G06F21/52 ,  G06F7/72 ,  G06F7/523

    CPC classification number: G06F21/52 ,  G06F7/523 ,  G06F7/72 ,  G06F7/723 ,  G06F2207/7242 ,  G06F2221/032

    Abstract: A method of protecting a modular calculation on a first number and a second number, executed by an electronic circuit, including the steps of: combining the second number with a third number to obtain a fourth number; executing the modular calculation on the first and fourth numbers, the result being contained in a first register or memory location; initializing a second register or memory location to the value of the first register or to one; and successively, for each bit at state 1 of the third number: if the corresponding bit of the fourth number is at state 1, multiplying the content of the second register or memory location by the inverse of the first number and placing the result in the first register or memory location, if the corresponding bit of the fourth number is at state 0, multiplying the content of the second register or memory location by the first number and placing the result in the first register or memory location.

    Protection of data processed by an encryption algorithm
    14.
    发明授权
    Protection of data processed by an encryption algorithm 有权

    公开(公告)号：US12158978B2

    公开(公告)日：2024-12-03

    申请号：US17850497

    申请日：2022-06-27

    Applicant: STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Simon Landry ,  Yanis Linge

    IPC: G06F21/72 ,  H04L9/00 ,  H04L9/06

    Abstract: The present disclosure relates to a method for protecting a first data item applied to a cryptographic algorithm, executed by a processor, wherein said algorithm is a per-round algorithm, with each round processing contents of first, second and third registers, the content of the second register being masked, during first parity rounds, by the content of a fourth register and the content of the third register being masked, during second parity rounds, by the content of a fifth register.

    Fault detection
    16.
    发明授权
    Fault detection 有权

    公开(公告)号：US11625504B2

    公开(公告)日：2023-04-11

    申请号：US17199279

    申请日：2021-03-11

    Applicant: STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Yanis Linge ,  Simon Landry

    IPC: G06F21/72

    Abstract: The present disclosure relates to a method of fault detection in an application, by an electronic circuit, of a first function to a message, including the steps of generating, from the message, a non-zero even number N of different first sets, each including P shares; applying, to the P shares of each first set, one or a plurality of second functions delivering, for each first set, a second set including Q images; and cumulating all the images, starting with at most Q-1 images selected from among the Q images of a same second set.

    Protection of the execution of cipher algorithms
    17.
    发明授权
    Protection of the execution of cipher algorithms 有权

    公开(公告)号：US11431491B2

    公开(公告)日：2022-08-30

    申请号：US16903209

    申请日：2020-06-16

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Thomas Sarno ,  Yanis Linge

    IPC: H04L9/08 ,  H04L9/06

    Abstract: Systems and methods for protecting secret or secure information involved in generation of ciphered data by circuitry. The circuitry includes data paths and key paths that operate to perform cipher operations to generate a plurality of key shares and a plurality of data shares using a key and data as input. The data and the key may be masked by at least one mask. The plurality of key shares may be generated using the key and a first mask. The plurality of data shares are generated using key shares, the data, and a second mask.

    Method and circuit for implementing a substitution table
    18.
    发明授权
    Method and circuit for implementing a substitution table 有权

    公开(公告)号：US11258579B2

    公开(公告)日：2022-02-22

    申请号：US16281887

    申请日：2019-02-21

    Applicant: STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Daniele Fronte ,  Yanis Linge ,  Thomas Ordas

    IPC: H04L9/06 ,  H04L9/00 ,  G06F21/72 ,  G09C1/00

    Abstract: A cryptographic circuit performs a substitution operation of a cryptographic algorithm based on a scrambled substitution table. For each set of one or more substitution operations of the cryptographic algorithm, the circuit performs a series of sets of one or more substitution operations of which: one is a real set of one or more substitution operations defined by the cryptographic algorithm, the real set of one or more substitution operations being based on input data modified by a real scrambling key; and one or more others are dummy sets of one or more substitution operations, each dummy set of one or more dummy substitution operations being based on input data modified by a different false scrambling key.

    Method for Randomly Modifying the Consumption Profile of a Logic Circuit, and Associated Device
    19.
    发明申请
    Method for Randomly Modifying the Consumption Profile of a Logic Circuit, and Associated Device 审中-公开

    公开(公告)号：US20190147771A1

    公开(公告)日：2019-05-16

    申请号：US16186820

    申请日：2018-11-12

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Alexandre Sarafianos ,  Thomas Ordas ,  Yanis Linge

    IPC: G09C1/00 ,  H03K19/003

    Abstract: In an embodiment, a circuit includes a supply terminal, a reference terminal, a logic circuit coupled between the supply terminal and the reference terminal, and an auxiliary circuit coupled to the logic circuit. The auxiliary circuit includes a plurality of switches configured to be controlled to produce random criterions. Each random criterion causes, on each transition of an output signal of the logic, an attenuation of a current flowing between a supply terminal of the circuit and a reference terminal of the circuit; or an increase of the current flowing between the supply terminal of the circuit and the reference terminal of the circuit; or an additional current flowing through the logic circuit on a current path not passing through the supply terminal; or no change in the current flowing between the supply terminal of the circuit and the reference terminal of the circuit.

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