公开(公告)号：US09490786B2

公开(公告)日：2016-11-08

申请号：US15088898

申请日：2016-04-01

Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

Inventor： Ni Zeng

IPC: H03B1/00 ,  H03K3/00 ,  H03K5/08 ,  H03K17/687

CPC classification number: H03K5/08 ,  G01R31/2621 ,  H03K3/011 ,  H03K17/08122 ,  H03K17/687

Abstract: A generator circuit is coupled to apply a control signal to the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

Abstract translation: 发电机电路被耦合以将控制信号施加到驱动输出节点的功率晶体管的栅极端子。 产生参考电压，其具有第一电压值作为控制信号的基准，并具有用于应力测试的第二，较高的电压值。 在参考电压和功率晶体管栅极之间提供钳位电路，以在两种模式下起作用。 在一种模式中，当发电机电路施加控制信号时，钳位电路施加第一钳位电压以钳位功率晶体管的栅极处的电压。 在另一种模式下，钳位电路在栅极压力测试期间施加第二个较高的钳位电压来钳位功率晶体管的栅极。

公开(公告)号：US20160218700A1

公开(公告)日：2016-07-28

申请号：US15088898

申请日：2016-04-01

Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

Inventor： Ni Zeng

IPC: H03K5/08 ,  H03K17/687

CPC classification number: H03K5/08 ,  G01R31/2621 ,  H03K3/011 ,  H03K17/08122 ,  H03K17/687

Abstract: A generator circuit is coupled to apply a control signal to the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

Abstract translation: 发电机电路被耦合以将控制信号施加到驱动输出节点的功率晶体管的栅极端子。 产生参考电压，其具有第一电压值作为控制信号的基准，并具有用于应力测试的第二，较高的电压值。 在参考电压和功率晶体管栅极之间提供钳位电路，以在两种模式下起作用。 在一种模式中，当发电机电路施加控制信号时，钳位电路施加第一钳位电压以钳位功率晶体管的栅极处的电压。 在另一种模式下，钳位电路在栅极压力测试期间施加第二个较高的钳位电压来钳位功率晶体管的栅极。

公开(公告)号：US09331672B2

公开(公告)日：2016-05-03

申请号：US14449232

申请日：2014-08-01

Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

Inventor： Ni Zeng

IPC: H03B1/00 ,  H03K3/00 ,  H03K3/011 ,  H03K17/687

CPC classification number: H03K5/08 ,  G01R31/2621 ,  H03K3/011 ,  H03K17/08122 ,  H03K17/687

Abstract: A generator circuit is coupled to apply a control signal the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

Abstract translation: 发电机电路被耦合以施加驱动输出节点的功率晶体管的栅极端子的控制信号。 产生参考电压，其具有第一电压值作为控制信号的基准，并具有用于应力测试的第二，较高的电压值。 在参考电压和功率晶体管栅极之间提供钳位电路，以在两种模式下起作用。 在一种模式中，当发电机电路施加控制信号时，钳位电路施加第一钳位电压以钳位功率晶体管的栅极处的电压。 在另一种模式下，钳位电路在栅极压力测试期间施加第二个较高的钳位电压来钳位功率晶体管的栅极。