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    CIRCUIT AND METHOD FOR CONTROLLED DISCHARGE OF A HIGH (POSITIVE OR NEGATIVE) VOLTAGE CHARGE PUMP
    13.
    发明申请
    CIRCUIT AND METHOD FOR CONTROLLED DISCHARGE OF A HIGH (POSITIVE OR NEGATIVE) VOLTAGE CHARGE PUMP 有权

    公开(公告)号：US20220158550A1

    公开(公告)日：2022-05-19

    申请号：US17494451

    申请日：2021-10-05

    Applicant: STMicroelectronics International N.V.

    Inventor： Vikas RANA ,  Neha DALAL

    IPC: H02M3/07

    Abstract: A charge pump circuit includes a first charge pump stage circuit coupled in series with a second charge pump stage circuit. A discharge circuit operates to discharge the charge pump circuit. The discharge circuit includes: a first switched circuit coupled to a first output of the first charge pump stage circuit and configured, when actuated, to discharge the first output; and a second switched circuit coupled to a second output of the second charge pump stage circuit and configured, when actuated, to discharge the second output. A discharge control circuit actuates the first switched discharge circuit to discharge the first output and then, after the first output is fully discharged, actuates the second switched discharge circuit to discharge the second output.

    CMOS OSCILLATOR HAVING STABLE FREQUENCY WITH PROCESS, TEMPERATURE, AND VOLTAGE VARIATION
    14.
    发明申请
    CMOS OSCILLATOR HAVING STABLE FREQUENCY WITH PROCESS, TEMPERATURE, AND VOLTAGE VARIATION 有权
    具有过程，温度和电压变化的稳定频率的CMOS振荡器

    公开(公告)号：US20160065220A1

    公开(公告)日：2016-03-03

    申请号：US14474091

    申请日：2014-08-30

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Vikas RANA ,  Ganesh RAJ R

    IPC: H03L1/00 ,  H03K3/03

    CPC classification number: H03L1/00 ,  H03K3/011 ,  H03K3/0315 ,  H03K3/0322 ,  H03K3/354 ,  H03L1/022 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/0997 ,  H03L7/148 ,  H03L7/18

    Abstract: A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage.

    Abstract translation: 时钟信号生成电路，被配置为生成具有在诸如电源电压，温度和处理时间的变化的操作条件的数量的变化中保持的频率的时钟信号。 在一个实施例中，PVT补偿的CMOS环形振荡器的所产生的时钟信号的频率扩展被配置为补偿电源电压的变化，以及通过处理和温度补偿电路对工艺和温度的变化。 PVT补偿的CMOS环形振荡器包括一个稳压电源，用于产生一个电源电压，该电源电压抵抗由于整个电源电压的变化引起的变化。

    CIRCUIT AND METHOD TO DETECT WORD-LINE LEAKAGE AND PROCESS DEFECTS IN NON-VOLATILE MEMORY ARRAY
    16.
    发明申请
    CIRCUIT AND METHOD TO DETECT WORD-LINE LEAKAGE AND PROCESS DEFECTS IN NON-VOLATILE MEMORY ARRAY 有权

    公开(公告)号：US20230008272A1

    公开(公告)日：2023-01-12

    申请号：US17837377

    申请日：2022-06-10

    Applicant: STMicroelectronics International N.V.

    Inventor： Vikas RANA ,  Vivek TYAGI

    IPC: G11C29/12 ,  G11C29/18 ,  G11C29/44 ,  G11C29/52

    Abstract: An integrated circuit die includes memory sectors, each memory sector including a memory array. The die includes a voltage regulator with a first transistor driven by an output voltage to thereby generate a gate voltage, the output voltage being generated based upon a difference between a constant current and a leakage current. A selection circuit selectively couples the gate voltage to a selected one of the plurality of memory sectors. A leakage detector circuit drives a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current, increases the variable current in response to the copy voltage being greater than the gate voltage, and asserts a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array.

    MEMORY CIRCUIT ARRANGEMENT FOR ACCURATE AND SECURE READ
    17.
    发明申请
    MEMORY CIRCUIT ARRANGEMENT FOR ACCURATE AND SECURE READ 有权

    公开(公告)号：US20210375333A1

    公开(公告)日：2021-12-02

    申请号：US17321344

    申请日：2021-05-14

    Applicant: STMicroelectronics International N.V.

    Inventor： Vikas RANA ,  Arpit VIJAYVERGIA

    IPC: G11C7/06

    Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.

    CHARGE PUMP CIRCUIT CONFIGURED FOR POSITIVE AND NEGATIVE VOLTAGE GENERATION
    18.
    发明申请
    CHARGE PUMP CIRCUIT CONFIGURED FOR POSITIVE AND NEGATIVE VOLTAGE GENERATION 有权

    公开(公告)号：US20210050778A1

    公开(公告)日：2021-02-18

    申请号：US16911967

    申请日：2020-06-25

    Applicant: STMicroelectronics International N.V.

    Inventor： Vikas RANA

    IPC: H02M3/07

    Abstract: A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.

    CHARGE PUMP REGULATION CIRCUIT TO INCREASE PROGRAM AND ERASE EFFICIENCY IN NONVOLATILE MEMORY
    19.
    发明申请
    CHARGE PUMP REGULATION CIRCUIT TO INCREASE PROGRAM AND ERASE EFFICIENCY IN NONVOLATILE MEMORY 审中-公开

    公开(公告)号：US20200235660A1

    公开(公告)日：2020-07-23

    申请号：US16742248

    申请日：2020-01-14

    Applicant: STMicroelectronics International N.V.

    Inventor： Vikas RANA ,  Shivam KALLA

    IPC: H02M3/07

    Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a control signal. A diode has an anode coupled to the first node and a cathode coupled to a second node. A current mirror arrangement sources a first current to the second node and sinks a second current from a third node. A comparator causes the control signal to direct the charge pump circuit to generate the charge pump output signal as having a voltage that ramps upwardly in magnitude (but negative in sign) if the voltage at the second node is greater than the voltage at the third node, and causes the control signal to direct the charge pump circuit to cease the ramping of the voltage of the charge pump output signal if the voltage at the second node is at least equal to the voltage at the third node.

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