公开(公告)号：US20200373398A1

公开(公告)日：2020-11-26

申请号：US16882293

申请日：2020-05-22

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Patrick FIORENZA ,  Fabrizio ROCCAFORTE ,  Mario Giuseppe SAGGIO

IPC: H01L29/423 ,  H01L29/872 ,  H01L29/16 ,  H01L27/06

Abstract: An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.

公开(公告)号：US20250015155A1

公开(公告)日：2025-01-09

申请号：US18764893

申请日：2024-07-05

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Patrick FIORENZA ,  Fabrizio ROCCAFORTE ,  Mario Giuseppe SAGGIO

IPC: H01L29/423 ,  H01L27/06 ,  H01L29/16 ,  H01L29/872

Abstract: An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.

公开(公告)号：US20230299173A1

公开(公告)日：2023-09-21

申请号：US18180680

申请日：2023-03-08

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone RASCUNA' ,  Fabrizio ROCCAFORTE ,  Gabriele BELLOCCHI ,  Marilena VIVONA

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/872 ,  H01L29/868 ,  H01L21/04 ,  H01L21/268 ,  H01L21/263 ,  H01L29/40

CPC classification number: H01L29/6606 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/2636 ,  H01L21/268 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/868 ,  H01L29/872

Abstract: Method for manufacturing an electronic device, comprising the steps of: forming, at a front side of a solid body of 4H-SiC having a first electrical conductivity, at least one implanted region having a second electrical conductivity opposite to the first electrical conductivity; forming, on the front side, a 3C-SiC layer; and forming, in the 3C-SiC layer, an ohmic contact region which extends through the entire thickness of the 3C-SiC layer, up to reaching the implanted region. A silicon layer may be present on the 3C-SiC layer; in this case, the ohmic contact also extends through the silicon layer.

公开(公告)号：US20210273087A1

公开(公告)日：2021-09-02

申请号：US17322528

申请日：2021-05-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Giuseppe GRECO ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L23/29 ,  H01L23/31

Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

公开(公告)号：US20180358458A1

公开(公告)日：2018-12-13

申请号：US16004272

申请日：2018-06-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Giuseppe GRECO ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7378

Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.