公开(公告)号：US20240243122A1

公开(公告)日：2024-07-18

申请号：US18416702

申请日：2024-01-18

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mario Giuseppe SAGGIO ,  Simone RASCUNÁ

IPC: H01L27/06 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L27/0629 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7806 ,  H01L29/872

Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.

公开(公告)号：US20240006527A1

公开(公告)日：2024-01-04

申请号：US18468499

申请日：2023-09-15

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Salvatore CASCINO ,  Alfio GUARNERA ,  Mario Giuseppe SAGGIO

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L29/402 ,  H01L29/0619 ,  H01L29/1608

Abstract: The present disclosure is directed to an electronic device including a semiconductor body having a first electrical conductivity and provided with a front side; an active area of the semiconductor body, accommodating the source and gate regions of the electronic device and configured to accommodate, in use, a conductive channel of the electronic device; and an edge region of the electronic device, surrounding the active area. The edge region accommodates at least in part: i) an edge termination region, having a second electrical conductivity opposite to the first electrical conductivity, extending into the semiconductor body at the front side; and ii) a gate connection terminal of conductive material, electrically coupled to the gate region, extending on the front side partially superimposed on the edge termination region and capacitively coupled with a portion of the semiconductor body adjacent and external to the edge termination region.

公开(公告)号：US20220344467A1

公开(公告)日：2022-10-27

申请号：US17741310

申请日：2022-05-10

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe SAGGIO ,  Edoardo ZANETTI ,  Alfio GUARNERA

IPC: H01L29/08 ,  H01L29/16

Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.

公开(公告)号：US20210328022A1

公开(公告)日：2021-10-21

申请号：US17225998

申请日：2021-04-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Simone RASCUNÁ ,  Mario Giuseppe SAGGIO ,  Giovanni FRANCO

IPC: H01L29/16 ,  H01L29/45 ,  H01L21/268

Abstract: A method for manufacturing a SiC-based electronic device, comprising the steps of: implanting, on a front side of a solid body made of SiC having a conductivity of an N type, dopant species of a P type thus forming an implanted region, which extends in the solid body starting from the front side and has a top surface coplanar with the front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region to temperatures comprised between 1500° C. and 2600° C. so as to form a carbon-rich electrical-contact region at the implanted region. The carbon-rich electrical-contact region forms an ohmic contact.

公开(公告)号：US20150349052A1

公开(公告)日：2015-12-03

申请号：US14824813

申请日：2015-08-12

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mario Giuseppe SAGGIO ,  Domenico MURABITO ,  Angelo MAGRI'

IPC: H01L29/06 ,  H01L29/739 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0634 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811

Abstract: An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.

Abstract translation: 一种用于高压器件的结构的实施例，其包括至少半导体衬底被第一导电类型的外延层覆盖，其中实现了多个柱结构，哪些柱结构包括高纵横比深度 所述外延层又被活性表面积覆盖，其中所述高电压器件被实现，所述列结构中的至少一个外部部分又由第二导电类型的硅外延层实现，所述硅外延层相反 比所述第一类型的导电性和具有使在所述列结构之外的所述外延层中的掺杂剂电荷平衡的掺杂剂电荷以及在所述外部部分内部实现的电介质填充部分，以便完全填充所述深沟槽。

公开(公告)号：US20250015155A1

公开(公告)日：2025-01-09

申请号：US18764893

申请日：2024-07-05

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Patrick FIORENZA ,  Fabrizio ROCCAFORTE ,  Mario Giuseppe SAGGIO

IPC: H01L29/423 ,  H01L27/06 ,  H01L29/16 ,  H01L29/872

Abstract: An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.

公开(公告)号：US20240203737A1

公开(公告)日：2024-06-20

申请号：US18395174

申请日：2023-12-22

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone RASCUNA' ,  Mario Giuseppe SAGGIO

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L21/045 ,  H01L29/1608 ,  H01L29/66053

Abstract: A manufacturing method of an anchorage element of a passivation layer, comprising: forming, in a semiconductor body made of SiC and at a distance from a top surface of the semiconductor body, a first implanted region having, along a first axis, a first maximum dimension; forming, in the semiconductor body, a second implanted region, which is superimposed to the first implanted region and has, along the first axis, a second maximum dimension smaller than the first maximum dimension; carrying out a process of thermal oxidation of the first implanted region and second implanted region to form an oxidized region; removing said oxidized region to form a cavity; and forming, on the top surface, the passivation layer protruding into the cavity to form said anchorage element fixing the passivation layer to the semiconductor body.

公开(公告)号：US20230097579A1

公开(公告)日：2023-03-30

申请号：US17945530

申请日：2022-09-15

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Mario Giuseppe SAGGIO ,  Alfio GUARNERA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/04 ,  H01L21/761 ,  H01L29/66

Abstract: A silicon carbide power device has: a die having a functional layer of silicon carbide and an edge area and an active area, surrounded by the edge area; gate structures formed on a top surface of the functional layer in the active area; and a gate contact pad for biasing the gate structures. The device also has an integrated resistor having a doped region, of a first conductivity type, arranged at the front surface of the functional layer in the edge area; wherein the integrated resistor defines an insulated resistance in the functional layer, interposed between the gate structures and the gate contact pad.

公开(公告)号：US20220384662A1

公开(公告)日：2022-12-01

申请号：US17818926

申请日：2022-08-10

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Simone RASCUNA' ,  Mario Giuseppe SAGGIO

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66

Abstract: A merged-PN-Schottky, MPS, diode includes an N substrate, an N-drift layer, a P-doped region in the drift layer, an ohmic contact on the P-doped region, a plurality of cells within the P-doped region and being portions of the drift layer where the P-doped region is absent, an anode metallization on the ohmic contact and on said cells, to form junction-barrier contacts and Schottky contacts respectively. The P-doped region has a grid-shaped layout separating from one another each cell and defining, together with the cells, an active area of the MPS diode. Each cell has a same geometry among quadrangular, quadrangular with rounded corners and circular; and the ohmic contact extends at the doped region with continuity along the grid-shaped layout.

公开(公告)号：US20220246729A1

公开(公告)日：2022-08-04

申请号：US17565165

申请日：2021-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe SAGGIO ,  Edoardo ZANETTI ,  Alessia Maria FRAZZETTO ,  Alfio GUARNERA ,  Cateno Marco CAMALLERI ,  Antonio Giuseppe GRIMALDI

IPC: H01L29/16 ,  H01L21/04 ,  H01L29/10 ,  H01L21/265

Abstract: A vertical conduction MOSFET device includes a body of silicon carbide, which has a first type of conductivity and a face. A superficial body region of a second type of conductivity has a first doping level and extends into the body to a first depth , and has a first width. A source region of the first type of conductivity extends into the superficial body region to a second depth, and has a second width. The second depth is smaller than the first depth and the second width is smaller than the first width. A deep body region of the second type of conductivity has a second doping level and extends into the body, at a distance from the face of the body and in direct electrical contact with the superficial body region, and the second doping level is higher than the first doping level.