公开(公告)号：US09754681B2

公开(公告)日：2017-09-05

申请号：US15446909

申请日：2017-03-01

Applicant: STMicroelectronics S.r.l.

Inventor： Ignazio Bruno Mirabella ,  Salvatore Pappalardo ,  Calogero Ribellino ,  Alessandro Nicolosi

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C11/4125 ,  G11C17/16 ,  H03K3/02335 ,  H03K19/00338 ,  H03K19/17764

Abstract: A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

公开(公告)号：US20150236683A1

公开(公告)日：2015-08-20

申请号：US14622322

申请日：2015-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Ignazio Bruno Mirabella ,  Francesco Pulvirenti

IPC: H03K5/125

CPC classification number: H03K5/125 ,  H03K5/2436

Abstract: A high voltage comparison circuit includes an input stage generating an intermediate signal as a result of a comparison between an input signal and a first voltage reference and an output stage configured to generate an output signal referenced to a second voltage reference (different from the first voltage reference) in response to the intermediate signal.

Abstract translation: 高电压比较电路包括作为输入信号和第一参考电压之间的比较的结果产生中间信号的输入级和被配置为产生参考第二参考电压的输出信号（不同于第一电压 参考）响应于中间信号。