METHOD OF MANUFACTURING SUBSTRATES FOR SEMICONDUCTOR DEVICES, CORRESPONDING SUBSTRATE AND SEMICONDUCTOR DEVICE

    公开(公告)号:US20230031682A1

    公开(公告)日:2023-02-02

    申请号:US17870455

    申请日:2022-07-21

    Inventor: Mauro MAZZOLA

    Abstract: A pre-molded substrate for semiconductor devices includes a sculptured electrically conductive (e.g., copper) laminar structure having spaces therein. The laminar structure includes one or more die pads having a first die pad surface configured to have semiconductor chips mounted thereon. A pre-mold material molded onto the laminar structure penetrates into the spaces therein and provides a laminar pre-molded substrate including the first die pad surface left exposed by the pre-mold material with the die pad(s) bordering on the pre-mold material. One or more stress-relief curved portions are provided at the periphery of one or more of the die pads. The stress-relief curved portions are configured to border on the pre-mold material over a smooth surface to effectively counter the formation of cracks in the pre-mold material as a result of the pre-molded substrate being bent.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, COMPONENT FOR USE THEREIN AND CORRESPONDING SEMICONDUCTOR DEVICE

    公开(公告)号:US20220199500A1

    公开(公告)日:2022-06-23

    申请号:US17550925

    申请日:2021-12-14

    Abstract: A leadframe includes a pattern of electrically-conductive formations with one or more sacrificial connection formations extending bridge-like between a pair of electrically-conductive formations. The sacrificial connection formation or formations are formed at one of the first surface and the second surface of the leadframe and have a thickness less than the leadframe thickness between the first surface and the second surface. A filling of electrically-insulating material is molded between the electrically-conductive formations of the leadframe, with electrically-insulating material molded between the connection formation(s) and the other surface of the leadframe. The sacrificial connection formation(s) counter deformation and displacement of parts during formation and pre-molding of the leadframe.

    PROCESS FOR MANUFACTURING A FLIP CHIP SEMICONDUCTOR PACKAGE AND A CORRESPONDING FLIP CHIP PACKAGE

    公开(公告)号:US20180374780A1

    公开(公告)日:2018-12-27

    申请号:US16007767

    申请日:2018-06-13

    Abstract: A process for manufacturing a semiconductor flip chip package and a corresponding flip chip package. The process comprises associating conducting bump pads to a face corresponding to an active side of one or more electronic dice, flipping the one or more electronic dice so that said face corresponding to an active side of one or more electronic dies is facing a leadframe carrying contacting pads in correspondence of said conducting bump pads, bonding said contacting pads to said conducting bump pads and encasing said one or more electronic dice in a casing by a molding operation. The process includes providing a leadframe having contacting pads presenting a recessed surface in correspondence of the position of said conducting bump pads.

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