公开(公告)号：US20210305134A1

公开(公告)日：2021-09-30

申请号：US17328933

申请日：2021-05-24

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fabio MARCHISI

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31

Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.

公开(公告)号：US20240203834A1

公开(公告)日：2024-06-20

申请号：US18594699

申请日：2024-03-04

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Fabio MARCHISI

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/4853 ,  H01L21/4889 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/3107 ,  H01L24/45 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/85455

Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.

公开(公告)号：US20190043787A1

公开(公告)日：2019-02-07

申请号：US16031998

申请日：2018-07-10

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fabio MARCHISI

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.

公开(公告)号：US20230245994A1

公开(公告)日：2023-08-03

申请号：US18102147

申请日：2023-01-27

Applicant: STMicroelectronics S.r.l.

Inventor： Mauro MAZZOLA ,  Fabio MARCHISI

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/40 ,  H01L23/49513 ,  H01L24/32 ,  H01L24/73 ,  H01L23/4952 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/40177 ,  H01L2224/32245 ,  H01L2224/73263 ,  H01L2224/40505 ,  H01L2224/83 ,  H01L2224/84801 ,  H01L2224/92246

Abstract: A semiconductor device semiconductor chip mounted to a leadframe that includes an electrically conductive pad. An electrically conductive clip is arranged in a bridge-like position between the semiconductor chip and the electrically conductive pad. The electrically conductive clip is soldered to the semiconductor chip and to the electrically conductive pad via soldering material applied at coupling surfaces facing towards the semiconductor chip and the electrically conductive pad. The device further includes a pair of complementary positioning formations formed by a cavity in the electrically conductive clip and a protrusion (such as a stud bump or a stack of stud bumps) formed in the electrically conductive pad. The complementary positioning formations are mutually engaged to retain the electrically conductive clip in the bridge-like position to avoid displacement during soldering.

公开(公告)号：US20220059369A1

公开(公告)日：2022-02-24

申请号：US17407612

申请日：2021-08-20

Applicant: STMicroelectronics S.r.l.

Inventor： Marco ROVITTO ,  Pierangelo MAGNI ,  Fabio MARCHISI

IPC: H01L21/56 ,  H01L21/67 ,  H01L21/48

Abstract: A semiconductor die is attached to a die pad of a leadframe. The semiconductor die attached to the die pad is arranged in a molding cavity between complementary first and second mold portions. Package material is injected into the molding cavity via at least one injection channel provided in one of the complementary first and second mold portions. Air is evacuated from the molding cavity via at least one air venting channel provided in the other of the complementary first and second mold portions. An exit from the at least one air venting channel may be blocked by a retractable stopper during the injection of the package material.

公开(公告)号：US20160315035A1

公开(公告)日：2016-10-27

申请号：US14969481

申请日：2015-12-15

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fabio MARCHISI

IPC: H01L23/495 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L23/49537 ,  H01L21/4821 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An electronic component, such as an integrated circuit, includes at least one circuit having coupled therewith electrical connections including a lead frame of electrically conductive material. The lead frame is produced by an additive process of conductive material, e.g., by 3D printing, by forming a three-dimensional structure of leads having overlapping surfaces with a gap therebetween.

Abstract translation: 诸如集成电路的电子部件包括至少一个电路，其具有耦合的电连接，其包括导电材料的引线框架。 引线框架通过导电材料的添加工艺，例如通过3D印刷，通过形成具有间隙的重叠表面的引线的三维结构来制造。

公开(公告)号：US20230245955A1

公开(公告)日：2023-08-03

申请号：US18101983

申请日：2023-01-26

Applicant: STMicroelectronics S.r.l.

Inventor： Mauro MAZZOLA ,  Fabio MARCHISI

IPC: H01L23/495 ,  B23K26/0622 ,  B23K26/21 ,  H01L23/00

CPC classification number: H01L23/4952 ,  B23K26/21 ,  B23K26/0622 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247

Abstract: A semiconductor device includes an electrically conductive clip arranged in a bridge-like position between a semiconductor integrated circuit chip and an electrically conductive pad of a leadframe. The electrically conductive clip is soldered to the semiconductor integrated circuit chip and to the electrically conductive pad via soldering material applied at coupling surfaces facing towards the semiconductor integrated circuit chip and the electrically conductive pad. Prior to soldering, the clip is immobilized in the desired bridge-like position via one of welding (such as laser welding) or gluing at dedicated immobilization areas.

公开(公告)号：US20190181076A1

公开(公告)日：2019-06-13

申请号：US16213540

申请日：2018-12-07

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Dario VITELLO ,  Fabio MARCHISI ,  Alberto ARRIGONI ,  Federico FREGO ,  Federico Giovanni ZIGLIOLI ,  Paolo CREMA

IPC: H01L23/495 ,  H01L21/48 ,  B26F1/38 ,  B23C3/13 ,  C23F1/02

Abstract: A method of producing leadframes for semiconductor devices comprises: providing a plurality of electrically-conductive plates, forming in the electrically conductive plates homologous passageway patterns according to a desired semiconductor device leadframe pattern, joining together the plurality of plates with the homologous passageway patterns formed therein mutually in register by producing a multilayered leadframe exhibiting the desired leadframe pattern and a thickness which is the sum of the thicknesses of the plates in the plurality of electrically-conductive plates.

公开(公告)号：US20190006191A1

公开(公告)日：2019-01-03

申请号：US16020757

申请日：2018-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio MARCHISI

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor product such as an integrated circuit includes a laminar plastic substrate having first and second opposed surfaces and through holes extending through the substrate, electrically and/or thermally conductive material balls inserted in the through holes at the first surface of the substrate, and one or more semiconductor chips mounted at the first surface of the substrate, the semiconductor chip(s) electrically and/or thermally coupled with electrically and/or thermally conductive material balls inserted in the through holes.