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公开(公告)号：US11581892B2
公开(公告)日：2023-02-14
申请号：US16738419
申请日：2020-01-09
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno
IPC: H03K17/687 , H01L41/04 , H03K4/02
Abstract: A method includes pre-charging a parasitic capacitance of a control node that is coupled to a control terminal of first and second transistors that have respective current paths that form a switched current path coupled between a load node and a storage node. Pre-charging the parasitic capacitance includes: making conductive a first auxiliary transistor that has a current path coupled between the storage node and the control node, or making conductive a second auxiliary transistor that has a current path coupled between the load node and the control node. The method further includes, after pre-charging the parasitic capacitance, making the switched current path conductive to couple the load node to the storage node.
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公开(公告)号：US11193952B2
公开(公告)日：2021-12-07
申请号：US16738459
申请日：2020-01-09
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno
Abstract: A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.
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公开(公告)号：US11146267B1
公开(公告)日：2021-10-12
申请号：US17106574
申请日：2020-11-30
Applicant: STMicroelectronics S.r.l.
Inventor： Franco Consiglieri , Pasquale Flora , Marco Zamprogno
IPC: H03B1/00 , H03K3/00 , H03K17/687 , G02B7/182
Abstract: A charge recovery driver is for a pair of loads, and includes first and second output nodes coupled to a pair of loads. During an initial phase, the first output node is grounded and the second output node is tied to the supply voltage. During a first phase, the first output node is coupled to the first tank capacitor and the second output node is coupled to the second tank capacitor. During a second phase, the first and second output nodes are coupled to one another. During a third phase, the second output node is coupled to the first tank capacitor and the first output node is coupled to the second tank capacitor. During a fourth phase, the first output node is coupled to the supply voltage and the second output node is coupled to ground. The third, second, and first phases are then repeated in that order.
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公开(公告)号：US10897234B2
公开(公告)日：2021-01-19
申请号：US16361930
申请日：2019-03-22
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno , Simone Zezza , Pasquale Flora
IPC: H03F3/45
Abstract: A method and apparatus for sensing a common mode feedback current are provided. The common mode feedback current may flow through a common mode resistive divider of a piezoresistive bridge. A first current mirror mirrors the common mode feedback current and provides a first mirrored common mode current. A current aggregation stage receives the first mirrored common mode current and determines a bridge current of the piezoresistive bridge based on the first mirrored common mode feedback current. A second current mirror may be used to mirror the first current mirror before determining the bridge current.
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公开(公告)号：US20200304085A1
公开(公告)日：2020-09-24
申请号：US16361930
申请日：2019-03-22
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno , Simone Zezza , Pasquale Flora
IPC: H03F3/45
Abstract: A method and apparatus for sensing a common mode feedback current are provided. The common mode feedback current may flow through a common mode resistive divider of a piezoresistive bridge. A first current mirror mirrors the common mode feedback current and provides a first mirrored common mode current. A current aggregation stage receives the first mirrored common mode current and determines a bridge current of the piezoresistive bridge based on the first mirrored common mode feedback current. A second current mirror may be used to mirror the first current mirror before determining the bridge current.
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Patent Agency Ranking
公开(公告)号：US11561237B2
公开(公告)日：2023-01-24
申请号：US17524474
申请日：2021-11-11
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno
Abstract: A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.
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公开(公告)号：US20220065893A1
公开(公告)日：2022-03-03
申请号：US17524474
申请日：2021-11-11
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno
Abstract: A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.
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公开(公告)号：US10778208B2
公开(公告)日：2020-09-15
申请号：US16680831
申请日：2019-11-12
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno , Alireza Tajfar
IPC: H03K17/041 , H03K17/687 , H03M1/06 , H03K17/0812 , H03K19/08 , H03M1/66 , G03B21/20
Abstract: A circuit includes a first transistor and a second transistor having respective control terminals coupled to receive first and second bias voltages. A first electronic switch is coupled in series with, and between current paths of the first and second transistors to provide an output current line between a circuit output node and ground. A second electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between a bias node and a charge transfer node in the output current line. A third electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between the charge transfer node and the control terminal of the second transistor.
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公开(公告)号：US20200233206A1
公开(公告)日：2020-07-23
申请号：US16738419
申请日：2020-01-09
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno
Abstract: In an embodiment, a method includes pre-charging a parasitic capacitance of a control node that is coupled to a control terminal of first and second transistors that have respective current paths that form a switched current path coupled between a load node and a storage node. Pre-charging the parasitic capacitance includes: making conductive a first auxiliary transistor that has a current path coupled between the storage node and the control node, or making conductive a second auxiliary transistor that has a current path coupled between the load node and the control node. The method further includes, after pre-charging the parasitic capacitance, making the switched current path conductive to couple the load node to the storage node.
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公开(公告)号：US10348258B2
公开(公告)日：2019-07-09
申请号：US15975505
申请日：2018-05-09
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno , Maurizio Bongiorni , Pasquale Flora
Abstract: A single-stage differential operational amplifier including an input stage formed by a pair of input transistors having control terminals connected to a respective first and second input, first conduction terminals coupled to a respective first and second output and second conduction terminals coupled to receive a polarization current. An output stage is formed by a pair of output transistors in diode configuration and having control terminals coupled to a relative first conduction terminal and connected to a respective first and second output, and second conduction terminals connected to a reference line. A coupling stage is interposed between the first conduction terminals of the output transistors and the first and second outputs to define the diode configuration of the output transistors and a gain value of the operational amplifier.
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