公开(公告)号：US20220138530A1

公开(公告)日：2022-05-05

申请号：US17572899

申请日：2022-01-11

Applicant: STMicroelectronics SA

Inventor： Philippe GALY ,  Thomas BEDECARRATS

IPC: G06N3/04 ,  G06N3/063 ,  H01L27/02 ,  G11C11/54

Abstract: An artificial-neuron device includes an integration-generation circuit coupled between an input at which an input signal is received and an output at which an output signal is delivered, and a refractory circuit inhibiting the integrator circuit after the delivery of the output signal. The refractory circuit is formed by a first MOS transistor having a first conduction-terminal coupled to a supply node, a second conduction-terminal coupled to a common node, and a control-terminal coupled to the output, and a second MOS transistor having a first conduction-terminal coupled to the input, a second conduction-terminal coupled to a reference node at which a reference voltage is received, and a control-terminal coupled to the common node. A resistive-capacitive circuit is coupled between the supply node and the reference node and having a tap coupled to the common node, with the inhibition duration being dependent upon a time constant of the resistive-capacitive circuit.

公开(公告)号：US20220121913A1

公开(公告)日：2022-04-21

申请号：US17499506

申请日：2021-10-12

Applicant: STMicroelectronics SA

Inventor： Valerian CINCON ,  Philippe GALY

IPC: G06N3/063 ,  H03K19/20 ,  H03K3/356

Abstract: An artificial neuron includes a first capacitive node of application of a membrane potential of the neuron. A first transistor is configured to discharge the first capacitive node. A second capacitive node is driven according to the membrane potential and delivers a potential for controlling the first transistor. A second transistor is configured to discharge the second capacitive node. The second transistor is controlled according to a potential present at the second capacitive node.

公开(公告)号：US20220037513A1

公开(公告)日：2022-02-03

申请号：US17375285

申请日：2021-07-14

Applicant: STMicroelectronics SA

Inventor： Philippe GALY

IPC: H01L29/739 ,  H01L27/105

Abstract: A cell includes a Z2-FET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.

公开(公告)号：US20210278288A1

公开(公告)日：2021-09-09

申请号：US17192425

申请日：2021-03-04

Applicant: STMicroelectronics SA

Inventor： Philippe GALY ,  Renan LETHIECQ

IPC: G01K7/22 ,  H01L27/12 ,  H01L29/78 ,  H01L29/10

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

公开(公告)号：US20230163117A1

公开(公告)日：2023-05-25

申请号：US18095728

申请日：2023-01-11

Applicant: STMicroelectronics SA

Inventor： Louise DE CONTI ,  Philippe GALY

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L27/0277 ,  H01L27/1203 ,  H01L29/7436

Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.

公开(公告)号：US20210278287A1

公开(公告)日：2021-09-09

申请号：US17192438

申请日：2021-03-04

Applicant: STMicroelectronics SA

Inventor： Philippe GALY ,  Renan LETHIECQ

IPC: G01K7/01 ,  H01C7/00 ,  G01K7/25 ,  G05F3/24

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

公开(公告)号：US20210020663A1

公开(公告)日：2021-01-21

申请号：US16926128

申请日：2020-07-10

Applicant: STMicroelectronics SA

Inventor： Philippe GALY ,  Thomas BEDECARRATS

IPC: H01L27/12

Abstract: An integrated circuit includes a MOS transistor that is located in and on a semiconductor film of a silicon-on-insulator (SOI) substrate. The SOI substrate has, below a buried insulator layer, a first back gate region and two first auxiliary regions that are located, respectively, below source and drain contact regions of the MOS transistor. The conductivity type of the two first auxiliary regions is the opposite the conductivity type of the first back gate region. The conductivity type of the two first auxiliary regions is identical to the conductivity type of the source and drain contact regions of the MOS transistor.

公开(公告)号：US20190181131A1

公开(公告)日：2019-06-13

申请号：US16216541

申请日：2018-12-11

Applicant: STMicroelectronics SA

Inventor： Philippe GALY ,  Louise DE CONTI

IPC: H01L27/02 ,  H02H9/04

Abstract: An electronic device for providing ESD protection is formed by a MOS transistor. the MOS transistor includes a source region and a drain region that are separated from each other by a channel-forming region. A first gate is located over the channel forming region. The drain region includes an extension region. A second gate is located over the extension region. The first and second gates are electrically connected to each other.

公开(公告)号：US20190164973A1

公开(公告)日：2019-05-30

申请号：US16199810

申请日：2018-11-26

Applicant: STMicroelectronics SA

Inventor： Hassan EL DIRANI ,  Thomas BEDECARRATS ,  Philippe GALY

IPC: H01L27/108 ,  G11C11/402 ,  G11C11/409

Abstract: A memory array includes memory cells of Z2-FET type arranged in rows and columns, wherein each memory cell includes a MOS-type selection transistor and a first region of a first conductivity type that is shared in common with a drain region of the first conductivity type of the selection transistors. The selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.