公开(公告)号：US20210134923A1

公开(公告)日：2021-05-06

申请号：US16915426

申请日：2020-06-29

Applicant: Samsung Display Co., LTD.

Inventor： Jee Hoon KIM ,  Shin Hyuk YANG ,  Jong Moo HUH ,  Dong Han KANG ,  Min Chul SHIN ,  Jun Ki LEE ,  Jae Seol CHO

IPC: H01L27/32 ,  H01L51/52

Abstract: A display device includes a substrate which includes a display area and a non-display area, a transistor disposed in the display area, a pad disposed in the non-display area, and an insulating layer which is disposed on the transistor and defines an opening which overlaps the pad in a plan view. The pad includes a main layer, a first auxiliary layer on the main layer, and a second auxiliary layer on the first auxiliary layer, and the second auxiliary layer defines the opening.

公开(公告)号：US20200373335A1

公开(公告)日：2020-11-26

申请号：US16991245

申请日：2020-08-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sung Ho KIM ,  Dong Won KIM ,  Jong Moo HUH

IPC: H01L27/12 ,  H01L27/32 ,  H01L29/786

Abstract: A thin film transistor array panel includes a substrate and a thin film transistor disposed on a surface of the substrate. The thin film transistor includes a semiconductor, a source electrode, and a drain electrode that are disposed on a same layer as one another. The semiconductor is between the source electrode and the drain electrode. The thin film transistor array panel further includes a buffer layer disposed between the semiconductor and the substrate and including an inorganic insulating material. The first edge of the buffer layer is substantially parallel to an adjacent edge of the semiconductor, a second edge of the buffer layer is substantially parallel to an adjacent edge of the source electrode, and a third edge of the buffer layer is substantially parallel to an adjacent edge of the drain electrode.

公开(公告)号：US20190148411A1

公开(公告)日：2019-05-16

申请号：US16232244

申请日：2018-12-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sung Ho KIM ,  Dong Won KIM ,  Jong Moo HUH

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/32

CPC classification number: H01L27/1214 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/3241 ,  H01L27/3244 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3274 ,  H01L29/78633 ,  H01L29/78648 ,  H01L29/7869

Abstract: A thin film transistor array panel includes a substrate and a thin film transistor disposed on a surface of the substrate. The thin film transistor includes a semiconductor, a source electrode, and a drain electrode that are disposed on a same layer as one another. The semiconductor is between the source electrode and the drain electrode. The thin film transistor array panel further includes a buffer layer disposed between the semiconductor and the substrate and including an inorganic insulating material. The first edge of the buffer layer is substantially parallel to an adjacent edge of the semiconductor, a second edge of the buffer layer is substantially parallel to an adjacent edge of the source electrode, and a third edge of the buffer layer is substantially parallel to an adjacent edge of the drain electrode.

公开(公告)号：US20180366532A1

公开(公告)日：2018-12-20

申请号：US16111210

申请日：2018-08-24

Applicant: Samsung Display Co., Ltd.

Inventor： Jae Hyun PARK ,  Sang Kyung LEE ,  Jong Moo HUH

IPC: H01L27/32 ,  H01L29/786 ,  H01L27/12 ,  H01L51/52 ,  H01L51/56 ,  H01L29/66

CPC classification number: H01L27/3276 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L51/5206 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/301 ,  H01L2251/308 ,  H01L2251/558

Abstract: A transistor substrate may include a base substrate, a data line, a conductive layer, a semiconductor layer, a gate electrode, and a pixel electrode. The data line may directly contact the base substrate. The conductive layer may directly contact the base substrate and may be spaced from the data line. The semiconductor layer may overlap the conductive layer, may be spaced from the conductive layer, and may include a source electrode and a drain electrode. The source electrode may be electrically connected to the data line. The gate electrode may overlap the semiconductor layer. The pixel electrode may be electrically connected to the drain electrode.

公开(公告)号：US20180097180A1

公开(公告)日：2018-04-05

申请号：US15483879

申请日：2017-04-10

Applicant: Samsung Display Co. Ltd.

Inventor： Hyuk Soon KWON ,  Chun Gi YOU ,  Sun PARK ,  Jong Moo HUH

IPC: H01L51/00 ,  H01L27/32 ,  H01L51/56 ,  G01R31/26 ,  G01R31/02

CPC classification number: H01L51/0031 ,  G09G3/006 ,  H01L27/3248 ,  H01L27/3276

Abstract: An organic light emitting display device includes a substrate, a semiconductor pattern disposed on the substrate, a conductive line disposed in a different layer from the semiconductor pattern, a pixel electrode disposed on the conductive line and on the semiconductor pattern, and a connection electrode disposed in a same layer as the pixel electrode. The connection electrode may be connected to the semiconductor pattern and the conductive line.

公开(公告)号：US20170323904A1

公开(公告)日：2017-11-09

申请号：US15434150

申请日：2017-02-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sung Ho KIM ,  Dong Won KIM ,  Jong Moo HUH

IPC: H01L27/12

CPC classification number: H01L27/1214 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/3241 ,  H01L27/3244 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3274 ,  H01L29/78633 ,  H01L29/78648 ,  H01L29/7869

Abstract: A thin film transistor array panel includes a substrate and a thin film transistor disposed on a surface of the substrate. The thin film transistor includes a semiconductor, a source electrode, and a drain electrode that are disposed on a same layer as one another. The semiconductor is between the source electrode and the drain electrode. The thin film transistor array panel further includes a buffer layer disposed between the semiconductor and the substrate and including an inorganic insulating material. The first edge of the buffer layer is substantially parallel to an adjacent edge of the semiconductor, a second edge of the buffer layer is substantially parallel to an adjacent edge of the source electrode, and a third edge of the buffer layer is substantially parallel to an adjacent edge of the drain electrode.