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公开(公告)号:US11049929B2
公开(公告)日:2021-06-29
申请号:US16804152
申请日:2020-02-28
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Kyungjin Jeon , Joonseok Park , Soyoung Koo , Myounghwa Kim , Eoksu Kim , Taesang Kim , Hyungjun Kim , Yeonkeon Moon , Geunchul Park , Sangwoo Sohn , Junhyung Lim , Hyelim Choi
Abstract: A display device includes: a substrate; a first thin film transistor and a second thin film transistor arranged over the substrate; a display element connected to the first thin film transistor; a wiring connected to the second thin film transistor and including a first wiring layer and a second wiring layer; a pattern insulating layer arranged between the first wiring layer and the second wiring layer; a planarization layer covering the wiring; and a connection electrode arranged on the planarization layer and connected to the first wiring layer and the second wiring layer respectively through a first contact hole and a second contact hole.
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公开(公告)号:US10658399B2
公开(公告)日:2020-05-19
申请号:US16515153
申请日:2019-07-18
Applicant: Samsung Display Co., Ltd.
Inventor: Jihun Lim , Jaybum Kim , Joonseok Park , Kyoungseok Son , Junhyung Lim
IPC: H01L29/49 , H01L29/788 , H01L29/786 , H01L27/12 , H01L27/32 , G02F1/1362 , G02F1/1368 , H01L29/66
Abstract: A transistor includes a semiconductor layer comprising a channel portion, a first contact portion and a second contact portion, a gate electrode facing the floating gate, and a floating gate disposed between the semiconductor layer and the gate electrode, the floating gate being insulated from the semiconductor layer and the gate electrode. The floating gate comprises an oxide semiconductor.
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公开(公告)号:US10593808B2
公开(公告)日:2020-03-17
申请号:US16108454
申请日:2018-08-22
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Joonseok Park , Jihun Lim , Myounghwa Kim , Taesang Kim , Yeonkeon Moon
IPC: H01L29/786 , H01L29/24 , H01L23/532 , H01L27/32 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423
Abstract: A thin film transistor includes an active layer over a substrate, a gate electrode over the active layer, a gate line connected with the gate electrode, and a gate insulation film between the active layer and the gate electrode. The active layer includes a channel region overlapping the gate electrode, and a drain region and a source region on respective sides of the channel region. A length of a straight line connecting the drain region and the source region by a shortest distance may be greater than a width of the gate line parallel to the straight line.
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