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公开(公告)号：US10367012B2
公开(公告)日：2019-07-30
申请号：US15657508
申请日：2017-07-24
发明人： Jihun Lim , Jaybum Kim , Joonseok Park , Kyoungseok Son , Junhyung Lim
IPC分类号： H01L29/49 , H01L29/788 , H01L29/786 , H01L27/12 , H01L27/32 , G02F1/1362 , G02F1/1368 , H01L29/66
摘要： A transistor includes a semiconductor layer comprising a channel portion, a first contact portion and a second contact portion, a gate electrode facing the floating gate, and a floating gate disposed between the semiconductor layer and the gate electrode, the floating gate being insulated from the semiconductor layer and the gate electrode. The floating gate comprises an oxide semiconductor.
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公开(公告)号：US10854837B2
公开(公告)日：2020-12-01
申请号：US16911525
申请日：2020-06-25
发明人： Jaybum Kim , Eoksu Kim , Kyoungseok Son , Junhyung Lim , Jihun Lim
摘要： A display device includes a base substrate, a first transistor, a second transistor, an organic light emitting diode, and a capacitor electrically connected to the first thin film transistor. The first transistor includes a first semiconductor pattern below a first interlayer insulation layer and a first control electrode above the first interlayer insulation layer and below a second interlayer insulation layer. The second transistor includes a second control electrode above the first interlayer insulation layer and below the second interlayer insulation layer. A second semiconductor pattern is above the second interlayer insulation layer.
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公开(公告)号：US10541336B2
公开(公告)日：2020-01-21
申请号：US15724600
申请日：2017-10-04
发明人： Junhyung Lim , Jaybum Kim , Kyoungseok Son , Jihun Lim
IPC分类号： H01L29/786 , H01L21/02 , H01L21/322 , H01L51/52 , H01L29/423 , H01L27/32 , H01L29/04 , H01L27/12
摘要： A semiconductor device may include a base substrate, a first thin-film transistor (“TFT”) provided on the base substrate, a second TFT provided on the base substrate, and a plurality of insulating layers provided on the base substrate to define at least one dummy hole that is not overlapped with the first and second TFTs. The first TFT may include a first input electrode, a first output electrode, a first control electrode, and a first semiconductor pattern including a crystalline semiconductor material, and the second TFT may include a second input electrode, a second output electrode, a second control electrode, and a second semiconductor pattern including an oxide semiconductor material. A shortest distance between the at least one dummy hole and the second semiconductor pattern may be equal to or shorter than 5 micrometers (μm), in a plan view.
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公开(公告)号：US10361260B2
公开(公告)日：2019-07-23
申请号：US15684452
申请日：2017-08-23
发明人： Jaybum Kim , Kyoungseok Son , Jihun Lim , Eoksu Kim , Junhyung Lim
IPC分类号： H01L27/32 , H01L27/12 , G09G3/3225 , G09G3/3266 , G09G3/3275 , H01L29/786
摘要： A semiconductor device includes a base substrate, a first transistor including a first semiconductor pattern, a first control electrode, a first input electrode, and a first output electrode, each of which is disposed on the base substrate, a second transistor including a second semiconductor pattern, a second control electrode, a second input electrode, and a second output electrode, and a plurality of insulating layers. A single first through part exposes the first control electrode and the first semiconductor pattern disposed on both sides of the first control electrode.
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公开(公告)号：US11751434B2
公开(公告)日：2023-09-05
申请号：US17453522
申请日：2021-11-04
发明人： Kyoungseok Son , Dohyun Kwon , Jonghan Jeong , Jonghyun Choi , Eoksu Kim , Jaybum Kim , Junhyung Lim , Jihun Lim
IPC分类号： H10K59/121 , G09G3/3225 , H10K59/124 , G09G3/3233 , H10K59/126 , G09G3/3266 , G09G3/3275 , H01L27/12 , H01L29/786
CPC分类号： H10K59/1213 , G09G3/3225 , G09G3/3233 , H10K59/124 , H10K59/1216 , G09G3/3266 , G09G3/3275 , G09G2300/0413 , G09G2300/0426 , G09G2310/08 , H01L27/1225 , H01L27/1248 , H01L27/1251 , H01L27/1255 , H01L29/7869 , H01L29/78633 , H01L29/78675 , H10K59/126
摘要： A semiconductor device includes a base substrate, a first transistor disposed on the base substrate, the first transistor including a first input electrode, a first output electrode, a first control electrode, and a first semiconductor pattern including a crystalline semiconductor, a second transistor disposed on the base substrate, the second transistor including a second input electrode, a second output electrode, a second control electrode, and a second semiconductor pattern including an oxide semiconductor, a plurality of insulating layers disposed on the base substrate, and an upper electrode disposed on the first control electrode with at least one insulating layer of the plurality of insulating layers interposed between the upper electrode and the first control electrode. The upper electrode overlaps the first control electrode and forms a capacitor with the first control electrode.
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公开(公告)号：US10658399B2
公开(公告)日：2020-05-19
申请号：US16515153
申请日：2019-07-18
发明人： Jihun Lim , Jaybum Kim , Joonseok Park , Kyoungseok Son , Junhyung Lim
IPC分类号： H01L29/49 , H01L29/788 , H01L29/786 , H01L27/12 , H01L27/32 , G02F1/1362 , G02F1/1368 , H01L29/66
摘要： A transistor includes a semiconductor layer comprising a channel portion, a first contact portion and a second contact portion, a gate electrode facing the floating gate, and a floating gate disposed between the semiconductor layer and the gate electrode, the floating gate being insulated from the semiconductor layer and the gate electrode. The floating gate comprises an oxide semiconductor.
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公开(公告)号：US10593808B2
公开(公告)日：2020-03-17
申请号：US16108454
申请日：2018-08-22
发明人： Joonseok Park , Jihun Lim , Myounghwa Kim , Taesang Kim , Yeonkeon Moon
IPC分类号： H01L29/786 , H01L29/24 , H01L23/532 , H01L27/32 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423
摘要： A thin film transistor includes an active layer over a substrate, a gate electrode over the active layer, a gate line connected with the gate electrode, and a gate insulation film between the active layer and the gate electrode. The active layer includes a channel region overlapping the gate electrode, and a drain region and a source region on respective sides of the channel region. A length of a straight line connecting the drain region and the source region by a shortest distance may be greater than a width of the gate line parallel to the straight line.
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公开(公告)号：US10340472B2
公开(公告)日：2019-07-02
申请号：US15657369
申请日：2017-07-24
发明人： Jaybum Kim , Eoksu Kim , Kyoungseok Son , Junhyung Lim , Jihun Lim
摘要： A display device includes a base substrate, a first transistor, a second transistor, an organic light emitting diode, and a capacitor electrically connected to the first thin film transistor. The first transistor includes a first semiconductor pattern below a first interlayer insulation layer and a first control electrode above the first interlayer insulation layer and below a second interlayer insulation layer. The second transistor includes a second control electrode above the first interlayer insulation layer and below the second interlayer insulation layer. A second semiconductor pattern is above the second interlayer insulation layer.
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公开(公告)号：US11575100B2
公开(公告)日：2023-02-07
申请号：US17082459
申请日：2020-10-28
发明人： Jaybum Kim , Eoksu Kim , Kyoungseok Son , Junhyung Lim , Jihun Lim
摘要： A display device includes a base substrate, a first transistor, a second transistor, an organic light emitting diode, and a capacitor electrically connected to the first thin film transistor. The first transistor includes a first semiconductor pattern below a first interlayer insulation layer and a first control electrode above the first interlayer insulation layer and below a second interlayer insulation layer. The second transistor includes a second control electrode above the first interlayer insulation layer and below the second interlayer insulation layer. A second semiconductor pattern is above the second interlayer insulation layer.
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公开(公告)号：US11430847B2
公开(公告)日：2022-08-30
申请号：US16820102
申请日：2020-03-16
发明人： Kyoungseok Son , Jaybum Kim , Eoksu Kim , Junhyung Lim , Jihun Lim
IPC分类号： H01L27/32 , H01L21/02 , H01L21/4757 , H01L29/66 , H01L29/786 , H01L27/12 , H01L49/02 , H01L29/24
摘要： A method of manufacturing a semiconductor device. A pre first semiconductor pattern having a crystalline semiconductor material is formed on a base substrate. A pre first insulation layer is formed on the pre first semiconductor pattern. A first semiconductor pattern is formed by defining a channel region in the pre first semiconductor pattern. A pre protection layer is formed on the pre first insulation layer. A pre second semiconductor pattern including an oxide semiconductor material is formed on the pre protection layer. A pre second insulation layer is formed on the pre second semiconductor pattern. The pre second insulation layer is patterned using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed. A second semiconductor pattern is formed by defining a channel region in the pre second semiconductor pattern. The pre protection layer has a material with a first etch selectivity that is different from a second etch selectivity of the second insulation layer with respect to the etching gas.
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