公开(公告)号：US20210057457A1

公开(公告)日：2021-02-25

申请号：US16890756

申请日：2020-06-02

Applicant: Samsung Display Co., Ltd.

Inventor： Jay Bum KIM ,  Myeong Ho KIM ,  Kyoung Seok SON ,  Seung Jun LEE ,  Seung Hun LEE ,  Jun Hyung LIM

IPC: H01L27/12 ,  H01L27/32

Abstract: A display device includes: a bending region including a bending peripheral opening passing through the first interlayer insulating film and the first gate insulating film and a bending opening in the bending peripheral opening and passing through the second interlayer insulating film and the buffer layer to expose the substrate, a first sidewall of the bending peripheral opening includes a side surface of the first interlayer insulating film and a side surface of the first gate insulating film, the second interlayer insulating film covers the first sidewall of the bending peripheral opening, the bending opening includes a second sidewall including a side surface of the buffer layer and a portion of a side surface of the second interlayer insulating film arranged with the side surface of the buffer layer, and the first via layer fills the bending opening.

公开(公告)号：US20190252478A1

公开(公告)日：2019-08-15

申请号：US16254297

申请日：2019-01-22

Applicant: Samsung Display Co., Ltd.

Inventor： Kyoung Seok SON ,  Jaybum KIM ,  Yeon Keon MOON ,  Jun Hyung LIM

IPC: H01L27/32

CPC classification number: H01L27/3262 ,  H01L27/1251 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3258

Abstract: An organic light emitting display device includes a substrate, a first semiconductor element, a second semiconductor element, an insulation layer structure, and a light emitting structure. The substrate has a first region and a second region that is adjacent to the first region. The insulation layer structure is disposed between a second gate electrode and a second active layer of the second semiconductor element. The insulation layer structure includes a first insulation layer having a first etching rate, a second insulation layer disposed on the first insulation layer and having a second etching rate that is greater than the first etching rate, and a third insulation layer disposed on the second insulation layer and having a third etching rate that is less than the second etching rate in a same etching process. The light emitting structure is disposed on the insulation layer structure.

公开(公告)号：US20170323905A1

公开(公告)日：2017-11-09

申请号：US15478386

申请日：2017-04-04

Applicant: Samsung Display Co., Ltd.

Inventor： Ji Hun LIM ,  Jong Baek SEON ,  Kyoung Seok SON ,  Eok Su KIM ,  Tae Sang KIM

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a substrate; a semiconductor layer disposed on the substrate; a gate electrode disposed on the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer to not overlap the gate electrode, wherein a first edge of the gate electrode is aligned with a second edge of the semiconductor layer in a direction that is perpendicular to the substrate.

公开(公告)号：US20220293640A1

公开(公告)日：2022-09-15

申请号：US17831285

申请日：2022-06-02

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jay Bum KIM ,  Myeong Ho KIM ,  Kyoung Seok SON ,  Seung Jun LEE ,  Seung Hun LEE ,  Jun Hyung LIM

IPC: H01L27/12 ,  H01L27/32

Abstract: A display device includes: a bending region including a bending peripheral opening passing through the first interlayer insulating film and the first gate insulating film and a bending opening in the bending peripheral opening and passing through the second interlayer insulating film and the buffer layer to expose the substrate, a first sidewall of the bending peripheral opening includes a side surface of the first interlayer insulating film and a side surface of the first gate insulating film, the second interlayer insulating film covers the first sidewall of the bending peripheral opening, the bending opening includes a second sidewall including a side surface of the buffer layer and a portion of a side surface of the second interlayer insulating film arranged with the side surface of the buffer layer, and the first via layer fills the bending opening.

公开(公告)号：US20210305354A1

公开(公告)日：2021-09-30

申请号：US17344860

申请日：2021-06-10

Applicant: Samsung Display Co., Ltd.

Inventor： Kyoung Seok SON ,  Myoung Hwa KIM ,  Jay Bum KIM ,  Seung Jun LEE ,  Seung Hun LEE ,  Jun Hyung LIM

IPC: H01L27/32 ,  G09G3/3258 ,  G09G3/3291 ,  H01L51/52 ,  H01L51/56

Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.

公开(公告)号：US20210050398A1

公开(公告)日：2021-02-18

申请号：US16877977

申请日：2020-05-19

Applicant: Samsung Display Co., LTD.

Inventor： Myeong Ho KIM ,  Jay Bum KIM ,  Kyoung Seok SON ,  Seung Jun LEE ,  Seung Hun LEE ,  Jun Hyung LIM

IPC: H01L27/32 ,  H01L51/56 ,  H01L29/786

Abstract: A display device and a method of manufacturing a display device are provided. A display device includes a first conductive layer on a first gate insulating film and including a first gate electrode and a first electrode of a capacitor connected to the first gate electrode, and a second conductive layer on the second interlayer insulating film and including a first and a second source/drain electrode, and a second electrode of the capacitor, the second electrode of the capacitor is in a trench structure in which the second interlayer insulating film is partially removed.

公开(公告)号：US20200099015A1

公开(公告)日：2020-03-26

申请号：US16562729

申请日：2019-09-06

Applicant: Samsung Display Co., Ltd.

Inventor： Joon Seok PARK ,  Kyoung Seok SON ,  Jun Hyung LIM ,  Masataka KANO

IPC: H01L51/56 ,  H01L51/00 ,  H01L27/32

Abstract: A display apparatus including a base substrate, a first thin film transistor disposed on the base substrate, a via insulation layer disposed on the first thin film transistor, and a light emitting structure disposed on the via insulation layer. The first thin film transistor includes a first gate electrode, an oxide semiconductor overlapped with the first gate electrode, and including tin (Sn), an etch stopper disposed on the oxide semiconductor and including an oxide semiconductor material which does not include tin (Sn), a first source electrode making contact with the oxide semiconductor, and a first drain electrode making contact with the oxide semiconductor, and spaced apart from the first source electrode.

公开(公告)号：US20180175076A1

公开(公告)日：2018-06-21

申请号：US15842424

申请日：2017-12-14

Applicant: Samsung Display Co., Ltd.

Inventor： Eok Su KIM ,  Jay Bum KIM ,  Kyoung Seok SON ,  Jun Hyung LIM

IPC: H01L27/12 ,  H01L29/786

Abstract: A transistor array panel according to an exemplary embodiment includes: a substrate; a first buffer layer positioned on the substrate; and a first transistor and a second transistor positioned on the substrate and separated from each other, wherein the first transistor includes a polycrystalline semiconductor positioned on the substrate, and a first gate electrode overlapping the polycrystalline semiconductor, the second transistor includes an oxide semiconductor positioned on the first buffer layer, and a second gate electrode overlapping the oxide semiconductor, the first buffer layer covers the first gate electrode, and the first buffer layer includes a silicon oxide.