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公开(公告)号：US20200161477A1
公开(公告)日：2020-05-21
申请号：US16752126
申请日：2020-01-24
Applicant: Samsung Display Co., Ltd.
Inventor： Ji Hun LIM , Joon Seok PARK , Jay Bum KIM , Jun Hyung LIM , Kyoung Seok SON
IPC: H01L29/786 , H01L27/12 , H01L29/423 , H01L29/66
Abstract: A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.
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公开(公告)号：US20180069132A1
公开(公告)日：2018-03-08
申请号：US15691207
申请日：2017-08-30
Applicant: Samsung Display Co., Ltd.
Inventor： Ji Hun LIM , Joon Seok PARK , Jay Bum KIM , Jun Hyung LIM , Kyoung Seok SON
IPC: H01L29/786 , H01L27/12
CPC classification number: H01L29/78648 , H01L27/1225 , H01L27/127 , H01L29/42384 , H01L29/66969 , H01L29/78621 , H01L29/78633 , H01L29/7869 , H01L2029/42388
Abstract: A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.
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公开(公告)号：US20230255077A1
公开(公告)日：2023-08-10
申请号：US18135550
申请日：2023-04-17
Applicant: Samsung Display Co., Ltd.
Inventor： Kyoung Seok SON , Myoung Hwa KIM , Jay Bum KIM , Seung Jun LEE , Seung Hun LEE , Jun Hyung LIM
IPC: H10K59/131 , G09G3/3258 , G09G3/3291 , H10K50/80 , H10K59/124 , H10K71/00
CPC classification number: H10K59/1315 , G09G3/3258 , G09G3/3291 , H10K50/80 , H10K59/124 , H10K71/00 , H10K59/1201
Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.
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公开(公告)号：US20220278135A1
公开(公告)日：2022-09-01
申请号：US17745427
申请日：2022-05-16
Applicant: Samsung Display Co., Ltd.
Inventor： Kyoung Seok SON , Myounghwa KIM , Jaybum KIM , Yeon Keon MOON , Masataka KANO
Abstract: A display apparatus includes a base substrate, a polysilicon active pattern disposed on the base substrate, including polycrystalline silicon, including a source region and a drain region each doped with impurities and a channel region between the source region and the drain region, and including indium, a first gate electrode overlapping the channel region, and a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region.
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公开(公告)号：US20210143239A1
公开(公告)日：2021-05-13
申请号：US17002113
申请日：2020-08-25
Applicant: Samsung Display Co., Ltd.
Inventor： Myeong Ho KIM , Jay Bum KIM , Kyoung Seok SON , Sun Hee LEE , Seung Jun LEE , Seung Hun LEE , Jun Hyung LIM
IPC: H01L27/32
Abstract: A display device includes a substrate, a first semiconductor pattern on the substrate and including a semiconductor layer of a first transistor, a first gate insulator on the substrate, a first conductive layer on the first gate insulator and including a first gate electrode of the first transistor and a first electrode of the capacitor connected to the first gate electrode of the first transistor, a first interlayer dielectric on the first gate insulator, a second semiconductor pattern on the first interlayer dielectric and including a semiconductor layer of a second transistor and a second electrode of the capacitor, a second gate insulator on the first interlayer dielectric, a second conductive layer on the second gate insulator and including a gate electrode of the second transistor and a third semiconductor pattern between the second semiconductor pattern and any one of the first conductive layer and the second conductive layer.
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Patent Agency Ranking
公开(公告)号：US20230090058A1
公开(公告)日：2023-03-23
申请号：US17836386
申请日：2022-06-09
Applicant: Samsung Display Co., Ltd.
Inventor： Myeong Ho KIM , Jay Bum KIM , Kyoung Seok SON , Seung Jun LEE , Seung Hun LEE , Jun Hyung LIM
IPC: H01L27/32
Abstract: Provided is display device comprising a substrate; a first semiconductor layer disposed on the substrate and having a plurality of transistors; a second semiconductor layer disposed on the first semiconductor layer and having a plurality of transistors; a first data conductive layer disposed on the second semiconductor layer; a first metal layer disposed on the first data conductive layer; and a second metal layer disposed on the first metal layer, wherein the first metal layer includes a first storage electrode and a first input electrode, the second metal layer includes a second storage electrode and a second input electrode, the first storage electrode and the second storage electrode configure a storage capacitor, and the first input electrode and the second input electrode configure an input capacitor.
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公开(公告)号：US20220262883A1
公开(公告)日：2022-08-18
申请号：US17735617
申请日：2022-05-03
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Jay Bum KIM , Myeong Ho KIM , Kyoung Seok SON , Seung Jun LEE , Seung Hun LEE , Jun Hyung LIM
Abstract: A display device includes a substrate, a first semiconductor pattern, a first gate insulating film covering the first semiconductor pattern, a first conductive layer and a second semiconductor pattern are on the first gate insulating film, a second gate insulating film on the second semiconductor pattern, a third gate insulating film covering the first gate insulating film and the second gate insulating film, a second conductive layer on the third gate insulating film, an interlayer insulating film covering the second conductive layer, and a third conductive layer on the interlayer insulating film, wherein the first and second semiconductor patterns respectively form semiconductor layers of the first and second transistors, wherein the first conductive layer includes a gate electrode of the first transistor and a first electrode of the capacitor, and wherein the second conductive layer includes a gate electrode of the second transistor and a second electrode of the capacitor.
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公开(公告)号：US20210066421A1
公开(公告)日：2021-03-04
申请号：US15930650
申请日：2020-05-13
Applicant: Samsung Display Co., Ltd.
Inventor： Kyoung Seok SON , Myeong Ho KIM , Jay Bum KIM , Seung Jun LEE , Seung Hun LEE , Jun Hyung LIM
Abstract: A display device includes a substrate, a first semiconductor layer on the substrate, a first gate insulating film on the first semiconductor layer, a first conductive layer on the first gate insulating film and including a first gate electrode and a first electrode of a capacitor connected to the first gate electrode, a second semiconductor layer on the first gate insulating film and at a different layer from the first semiconductor layer, a second gate insulating film on the first conductive layer and the second semiconductor layer, a second conductive layer on the second gate insulating film and including a second gate electrode and a second electrode of the capacitor, a second interlayer insulating film on the second conductive layer, and a third conductive layer on the second interlayer insulating film and including a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode.
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公开(公告)号：US20190312061A1
公开(公告)日：2019-10-10
申请号：US16371433
申请日：2019-04-01
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Kyoung Seok SON , Myounghwa KIM , Jaybum KIM , Yeon Keon MOON , Masataka KANO
Abstract: A display apparatus includes a base substrate, a polysilicon active pattern disposed on the base substrate, including polycrystalline silicon, including a source region and a drain region each doped with impurities and a channel region between the source region and the drain region, and including indium, a first gate electrode overlapping the channel region, and a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region.
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公开(公告)号：US20210104590A1
公开(公告)日：2021-04-08
申请号：US16915049
申请日：2020-06-29
Applicant: Samsung Display Co., Ltd.
Inventor： Jay Bum KIM , Myeong Ho KIM , Kyoung Seok SON , Seung Jun LEE , Seung Hun LEE , Jun Hyung LIM
Abstract: A display device includes a substrate, a first semiconductor pattern, a first gate insulating film covering the first semiconductor pattern, a first conductive layer and a second semiconductor pattern are on the first gate insulating film, a second gate insulating film on the second semiconductor pattern, a third gate insulating film covering the first gate insulating film and the second gate insulating film, a second conductive layer on the third gate insulating film, an interlayer insulating film covering the second conductive layer, and a third conductive layer on the interlayer insulating film, wherein the first and second semiconductor patterns respectively form semiconductor layers of the first and second transistors, wherein the first conductive layer includes a gate electrode of the first transistor and a first electrode of the capacitor, and wherein the second conductive layer includes a gate electrode of the second transistor and a second electrode of the capacitor.
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