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公开(公告)号：US20170323905A1
公开(公告)日：2017-11-09
申请号：US15478386
申请日：2017-04-04
发明人： Ji Hun LIM , Jong Baek SEON , Kyoung Seok SON , Eok Su KIM , Tae Sang KIM
IPC分类号： H01L27/12 , H01L29/66 , H01L29/786
CPC分类号： H01L27/1225 , H01L27/124 , H01L27/1259 , H01L29/66969 , H01L29/78633 , H01L29/7869
摘要： A thin film transistor array panel includes: a substrate; a semiconductor layer disposed on the substrate; a gate electrode disposed on the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer to not overlap the gate electrode, wherein a first edge of the gate electrode is aligned with a second edge of the semiconductor layer in a direction that is perpendicular to the substrate.
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公开(公告)号：US20140084293A1
公开(公告)日：2014-03-27
申请号：US13798811
申请日：2013-03-13
发明人： Byung Du AHN , Jung Hwa KIM , Ji Hun LIM , Je Hun LEE , Dae Hwan KIM , Hyun Kwang JUNG
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/66969 , H01L29/78693 , H01L33/387
摘要： A thin film transistor array panel includes a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a source electrode and a drain electrode on the semiconductor layer and facing each other, a floating metal layer between the source electrode and the drain electrode, and a passivation layer covering the source electrode, the drain electrode, and the floating metal layer. The floating metal layer is electrically floating.
摘要翻译： 薄膜晶体管阵列面板包括基板，基板上的栅极电极，栅电极上的栅极绝缘层，栅极绝缘层上的半导体层，半导体层上的源电极和漏电极，并面对彼此 ，源电极和漏电极之间的浮动金属层，以及覆盖源电极，漏电极和浮置金属层的钝化层。 浮动金属层电浮动。
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公开(公告)号：US20200161477A1
公开(公告)日：2020-05-21
申请号：US16752126
申请日：2020-01-24
发明人： Ji Hun LIM , Joon Seok PARK , Jay Bum KIM , Jun Hyung LIM , Kyoung Seok SON
IPC分类号： H01L29/786 , H01L27/12 , H01L29/423 , H01L29/66
摘要： A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.
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公开(公告)号：US20180069132A1
公开(公告)日：2018-03-08
申请号：US15691207
申请日：2017-08-30
发明人： Ji Hun LIM , Joon Seok PARK , Jay Bum KIM , Jun Hyung LIM , Kyoung Seok SON
IPC分类号： H01L29/786 , H01L27/12
CPC分类号： H01L29/78648 , H01L27/1225 , H01L27/127 , H01L29/42384 , H01L29/66969 , H01L29/78621 , H01L29/78633 , H01L29/7869 , H01L2029/42388
摘要： A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.
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5.发明申请THIN FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND LIQUID CRYSTAL DISPLAY PANEL HAVING THE SAME 有权薄膜晶体管基板，其制造方法和具有该薄膜晶体管的液晶显示面板公开(公告)号：US20160133754A1
公开(公告)日：2016-05-12
申请号：US14661470
申请日：2015-03-18
发明人： Yeon Keon MOON , Masataka KANO , Sung-Hoon YANG , Ji Hun LIM , So Young KOO , Myoung Hwa KIM , Jun Hyung LIM
IPC分类号： H01L29/786 , G02F1/1368 , H01L29/66
CPC分类号： H01L29/78645 , G02F1/1368 , G02F2001/13685 , H01L29/42384 , H01L29/66742 , H01L29/78642 , H01L29/78648
摘要： A thin film transistor substrate includes a substrate, a bottom gate on the substrate, a first insulating layer on the substrate and on the bottom gate, a drain on the first insulating layer, a source on the first insulating layer, the source including a first source at a first side of the drain and a second source at a second side of the drain, an active layer on the first insulating layer, the active layer including a first active layer contacting the drain and the first source and a second active layer contacting the drain and the second source, a second insulating layer on the drain, the source, and the active layer, and a top gate on the second insulating layer.
摘要翻译： 薄膜晶体管衬底包括衬底，衬底上的底栅，衬底上的第一绝缘层和底栅，第一绝缘层上的漏极，第一绝缘层上的源，源包括第一绝缘层 漏极的第一侧的源极和在漏极的第二侧的第二源极，在第一绝缘层上的有源层，有源层包括接触漏极和第一源极的第一有源层和与第一源极接触的第二有源层 漏极和第二源极，漏极，源极和有源层上的第二绝缘层，以及第二绝缘层上的顶栅极。
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公开(公告)号：US20150171226A1
公开(公告)日：2015-06-18
申请号：US14635732
申请日：2015-03-02
发明人： Byung Du AHN , Ji Hun LIM , Jun Hyung LIM , Dae Hwan KIM , Jae Hyeong KIM , Je Hun LEE , Hyun Kwang JUNG
IPC分类号： H01L29/786 , H01L27/12
CPC分类号： H01L29/78606 , H01L21/28 , H01L27/124 , H01L29/786 , H01L29/78678 , H01L29/7869 , H01L29/78696
摘要： A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.
摘要翻译： 薄膜晶体管显示面板a包括透明基板; 位于所述基板上的栅电极; 位于所述栅电极上的栅极绝缘层; 位于所述栅绝缘层上并包括沟道区的半导体层; 位于半导体层上且彼此面对的源电极和漏电极; 以及钝化层，被配置为覆盖所述源电极，所述漏电极和所述半导体层，其中所述半导体层包括在所述源电极和所述栅电极之间的相对较厚的第一部分，以及在所述漏电极和所述半导体层之间的相对较薄的第二部分 栅电极重叠，相对较厚的第一部分足够厚，以便如果第一部分与第二部分一样薄，则基本上可以减少否则可能在栅极电极到栅介质界面处发生的电荷捕获现象。
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公开(公告)号：US20160365368A1
公开(公告)日：2016-12-15
申请号：US14963769
申请日：2015-12-09
发明人： Masataka KANO , Ji Hun LIM , Yeon Keon MOON , Jun Hyung LIM , So Young KOO , Myoung Hwa KIM
IPC分类号： H01L27/12 , H01L29/788 , H01L29/786 , H01L29/66 , H01L29/417 , H01L29/423
CPC分类号： H01L27/1248 , H01L27/124 , H01L27/1259 , H01L29/41733 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/66969 , H01L29/78606 , H01L29/78648 , H01L29/7869 , H01L29/788
摘要： A thin-film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a first self-assembled monolayer disposed on the first gate electrode, a gate insulating layer disposed on the first self-assembled monolayer, a semiconductor disposed on the gate insulating layer, a drain electrode overlapping the semiconductor, the drain electrode being separated from and facing a source electrode with respect to the semiconductor, a first interlayer insulating layer disposed on the source electrode and the drain electrode, a second self-assembled monolayer disposed on the first interlayer insulating layer, a second gate electrode disposed on the second self-assembled monolayer, a second interlayer insulating layer disposed on the second gate electrode, and a pixel electrode disposed on the second interlayer insulating layer and connected to the drain electrode.
摘要翻译： 薄膜晶体管阵列面板包括基板，设置在基板上的第一栅极电极，设置在第一栅电极上的第一自组装单层，设置在第一自组装单层上的栅极绝缘层，设置在第一自组装单层上的半导体 所述栅极绝缘层，与所述半导体重叠的漏电极，所述漏电极相对于所述半导体分离并面对源电极，设置在所述源电极和所述漏电极上的第一层间绝缘层，第二自组装单层 设置在第一层间绝缘层上的第二栅电极，设置在第二自组装单层上的第二栅电极，设置在第二栅电极上的第二层间绝缘层，以及设置在第二层间绝缘层上并连接到漏极的像素电极 。
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公开(公告)号：US20140103332A1
公开(公告)日：2014-04-17
申请号：US13789335
申请日：2013-03-07
发明人： Byung Du AHN , Ji Hun LIM , Jun Hyung LIM , Dae Hwan KIM , Jae Hyeong KIM , Je Hun LEE , Hyun Kwang JUNG
IPC分类号： H01L29/786
CPC分类号： H01L29/78606 , H01L21/28 , H01L27/124 , H01L29/786 , H01L29/78678 , H01L29/7869 , H01L29/78696
摘要： A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.
摘要翻译： 薄膜晶体管显示面板a包括透明基板; 位于所述基板上的栅电极; 位于所述栅电极上的栅极绝缘层; 位于所述栅绝缘层上并包括沟道区的半导体层; 位于半导体层上且彼此面对的源电极和漏电极; 以及钝化层，被配置为覆盖所述源电极，所述漏电极和所述半导体层，其中所述半导体层包括在所述源电极和所述栅电极之间的相对较厚的第一部分，以及在所述漏电极和所述半导体层之间的相对较薄的第二部分 栅电极重叠，相对较厚的第一部分足够厚，以便如果第一部分与第二部分一样薄，则基本上可以减少否则可能在栅极电极到栅介质界面处发生的电荷捕获现象。
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