公开(公告)号：US11672146B2

公开(公告)日：2023-06-06

申请号：US17373602

申请日：2021-07-12

Applicant: Samsung Display Co., Ltd.

Inventor： Jae Bum Han ,  Moon Sung Kim ,  Young Gil Park ,  Soo Im Jeong

IPC: H01L29/08 ,  H01L27/32 ,  G09G3/3233 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/3262 ,  H01L27/323 ,  G09G3/3233 ,  G09G2300/0426 ,  H01L27/1222 ,  H01L27/1274 ,  H01L29/66757 ,  H01L29/78675 ,  H01L2227/323

Abstract: A display device includes: a substrate; and a semiconductor layer disposed on the substrate, and including a first area, a second area, and a third area that are sequentially positioned by dividing the semiconductor layer into three areas in a thickness direction of the semiconductor layer, wherein the semiconductor layer includes polycrystalline silicon, a concentration of fluorine contained in the semiconductor layer has a first peak value in the first area and a second peak value in the third area, and the first peak value of the concentration of the fluorine in the semiconductor layer is about 30% or less of the second peak value of the concentration of the fluorine in the semiconductor layer.

公开(公告)号：US20180040739A1

公开(公告)日：2018-02-08

申请号：US15662502

申请日：2017-07-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： SUNG WOOK WOO ,  Chang Ho Lee ,  Kyung Lae Rho ,  Doo Hyoung Lee ,  Sung Chan Jo ,  Sang Woo Sohn ,  Sang Won Shin ,  Soo Im Jeong ,  Chang Yong Jeong

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/10 ,  H01L29/04

CPC classification number: H01L29/78693 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/247 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A transistor includes a gate electrode, a semiconductor layer overlapping the gate electrode, the semiconductor layer including an oxide semiconductor, and a source electrode and a drain electrode spaced apart from the source electrode, wherein the source and drain electrodes are connected to the semiconductor layer. The semiconductor layer includes a plurality of layers, wherein a crystallinity of a layer of the plurality of layers of the semiconductor layer is a ratio of a crystalline oxide semiconductor, included in the layer of the plurality of layers of the semiconductor layer, to an amorphous oxide semiconductor, included in the layer of the plurality of layers of the semiconductor layer. A first layer of the plurality of layers of the semiconductor layer has a different crystallinity with respect to a second layer of the plurality of layers of the semiconductor layer.