公开(公告)号：US20210209997A1

公开(公告)日：2021-07-08

申请号：US17209068

申请日：2021-03-22

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Beom Jun KIM ,  Seong Yeol SYN ,  Bong-Jun LEE ,  You Mee HYUN

IPC: G09G3/20 ,  G09G3/36 ,  G11C19/28

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

公开(公告)号：US20160358573A1

公开(公告)日：2016-12-08

申请号：US15012612

申请日：2016-02-01

Applicant: Samsung Display Co. Ltd.

Inventor： Noboru TAKEUCHI ,  Min Soo KANG ,  Beom Jun KIM ,  Yoon Ho KIM ,  Seong Yeol SYN ,  Hong Woo LEE

IPC: G09G3/36 ,  H03K17/687

CPC classification number: G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0289 ,  G09G2310/08 ,  G11C19/28

Abstract: A gate driving circuit is provided. A gate driving circuit comprises a pull-up control unit including a control transistor, a pull-up unit, a carry unit which outputs a clock signal into a kth carry signal and a pull-down unit which pulls down a control node to an off voltage, wherein the control transistor includes one electrode and the other electrode connected to the control node, the one electrode and the other electrode being disposed on a gate electrode such that the one electrode and the other electrode being insulated from the gate electrode, wherein the gate electrode and the other electrode are disposed not to be overlapped with each other, and a distance between an upper surface of the gate electrode and a lower surface of the one electrode is longer than that of the upper surface of the gate electrode and a lower surface of the other electrode.

Abstract translation: 提供了栅极驱动电路。 栅极驱动电路包括上拉控制单元，其包括控制晶体管，上拉单元，将时钟信号输出到第k个进位信号的进位单元和将控制节点拉低关断的下拉单元 电压，其中所述控制晶体管包括一个电极，而另一个电极连接到所述控制节点，所述一个电极和所述另一个电极设置在栅电极上，使得所述一个电极和所述另一个电极与所述栅电极绝缘，其中， 栅电极和另一电极彼此不重叠设置，并且栅电极的上表面和一个电极的下表面之间的距离比栅电极的上表面的距离长，下电极的下表面 另一个电极的表面。