公开(公告)号：US20230252932A1

公开(公告)日：2023-08-10

申请号：US18135212

申请日：2023-04-17

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Beom Jun KIM ,  Seong Yeol SYN ,  Bong-Jun LEE ,  You Mee HYUN

IPC: G09G3/20 ,  G09G3/36 ,  G11C19/28

CPC classification number: G09G3/2092 ,  G09G3/3648 ,  G09G3/3677 ,  G11C19/28 ,  G09G2310/0286 ,  G09G2300/0809

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

公开(公告)号：US20220114924A1

公开(公告)日：2022-04-14

申请号：US17468089

申请日：2021-09-07

Applicant: Samsung Display Co., LTD.

Inventor： Seung-Kyu LEE ,  Sang Seop KUM ,  Beom Jun KIM

IPC: G09F9/302 ,  G06F3/14

Abstract: A display panel alignment device of a tiling display includes a frame including panel seating portions and a gap around the panel seating portions, and a panel movement controller disposed in each of the panel seating portions. A display panel is disposed in each of the panel seating portions. The panel movement controller controls a movement of the display panel in a front direction, a rear direction, a left direction, and a right direction, and controls rotation of the display panel.

公开(公告)号：US20200020269A1

公开(公告)日：2020-01-16

申请号：US16583018

申请日：2019-09-25

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Beom Jun KIM ,  Seong Yeol SYN ,  Bong-Jun LEE ,  You Mee HYUN

IPC: G09G3/20 ,  G11C19/28 ,  G09G3/36

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

公开(公告)号：US20210240045A1

公开(公告)日：2021-08-05

申请号：US17066576

申请日：2020-10-09

Applicant: Samsung Display Co., Ltd.

Inventor： Gwon-Heon RYU ,  Yang Gyu JANG ,  Kook Hyun CHOI ,  Beom Jun KIM ,  Hyung Gi JUNG

IPC: G02F1/1362 ,  H01L27/12 ,  G02F1/1368

Abstract: The present disclosure relates to a display device including a substrate, a gate line on the substrate, a data line crossing the gate line, a pixel connected to the gate line and the data line, and a dummy data line disposed at an edge on the substrate and crossing the gate line, wherein the dummy data line includes openings that is disposed on a portion that is near an overlapping portion with the gate line, and portions of the dummy data line separated by the openings are electrically insulated from each other.

公开(公告)号：US20160189654A1

公开(公告)日：2016-06-30

申请号：US14715792

申请日：2015-05-19

Applicant: Samsung Display Co., LTD.

Inventor： Yoon Ho KIM ,  Beom Jun KIM ,  Geun Hyuk CHOI ,  Noboru TAKEUCHI ,  Yong Soon LEE ,  Jong Hwan LEE ,  Hong-Woo LEE ,  Yong-Sik HWANG

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G09G3/3696 ,  G09G2310/08 ,  G09G2320/041 ,  G09G2320/043

Abstract: A display panel includes: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels; a gate driver connected to the plurality of gate lines to apply a gate signal voltage; a data driver connected to the plurality of data lines to apply a data voltage and a negative data voltage; and a gate voltage divider for generating a gate signal voltage including gate-on and gate-off voltages to provided it to the gate driver. The gate voltage divider adjusts the gate-off voltage in accordance with a driving time of the display panel and a temperature of the display panel.

Abstract translation: 显示面板包括：显示面板，包括多条栅极线，多条数据线和多个像素; 连接到所述多个栅极线以施加栅极信号电压的栅极驱动器; 连接到所述多条数据线的数据驱动器，以施加数据电压和负数据电压; 以及栅极分压器，用于产生包括栅极导通和栅极截止电压的栅极信号电压，以将其提供给栅极驱动器。 栅极分压器根据显示面板的驱动时间和显示面板的温度调节栅极截止电压。

公开(公告)号：US20220254310A1

公开(公告)日：2022-08-11

申请号：US17728584

申请日：2022-04-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kang Nam KIM ,  You Mee HYUN ,  Beom Jun KIM ,  Jong Hwan LEE ,  Sung Hoon LIM ,  Duc Han CHO

IPC: G09G3/3266 ,  G09G3/20 ,  G11C19/28 ,  G09G3/36

Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.

公开(公告)号：US20220102322A1

公开(公告)日：2022-03-31

申请号：US17222394

申请日：2021-04-05

Applicant: Samsung Display Co., LTD.

Inventor： Sang Seop KUM ,  Beom Jun KIM ,  Seung Kyu LEE

IPC: H01L25/075 ,  H01L23/544 ,  H01L33/50 ,  H01L33/62 ,  H01L33/58 ,  H01L27/12

Abstract: A tiled display device includes a first display device and a second display device, each of the first display and the second display including a display area and a non-display area. The first display device and the second display device are bonded to each other. The first display device includes an alignment key area and a lower electrode layer. The alignment key area performs an alignment key function when a process is performed on the tiled display device. The lower electrode layer includes a first lower electrode layer and a second lower electrode layer. The first lower electrode layer surrounds the display area of the first display device and the second lower electrode layer is disposed in the alignment key area.

公开(公告)号：US20160171950A1

公开(公告)日：2016-06-16

申请号：US14742915

申请日：2015-06-18

Applicant: Samsung Display Co., Ltd.

Inventor： Duc-Han CHO ,  Kang Nam KIM ,  Beom Jun KIM ,  You Mee HYUN

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3648 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/287

Abstract: A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.

Abstract translation: 显示装置包括：多个像素; 连接到所述多个像素的多个栅极线; 连接到栅极线的栅极线的输出端子; 连接到第一节点的第一晶体管，第一时钟信号输入端和输出端; 连接到第二时钟信号输入端子的第二晶体管，低电平电源电压和输出端子; 连接到第二节点的第三晶体管，低电平电源电压和第一节点; 连接到第一正向输入端子的第四晶体管，低电平电源电压和第二节点; 以及与第一反向输入端子，低电平电源电压和第二节点连接的第五晶体管。

公开(公告)号：US20140267214A1

公开(公告)日：2014-09-18

申请号：US14203272

申请日：2014-03-10

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Beom Jun KIM ,  Seong Yeol SYN ,  Bong-Jun LEE ,  You Mee HYUN

IPC: G09G3/36

CPC classification number: G09G3/2092 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G11C19/28

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

Abstract translation: 提供显示面板。 显示面板包括包括栅线和数据线的显示区域，以及连接到栅极线的端子的栅极驱动器。 栅极驱动器包括集成在衬底上的多个级，并且每个级包括逆变器单元，输出单元和Q结点稳定单元。 输出单元包括第一晶体管和第一电容器，其中第一晶体管包括用于接收时钟信号的输入端子，连接到节点Q的控制端子和连接到栅极电压输出端子的输出端子以输出栅极 电压。 当输出单元输出栅极导通电压时，Q节点稳定单元中的晶体管的Vgs电压具有等于或小于0V的值。

公开(公告)号：US20170140698A1

公开(公告)日：2017-05-18

申请号：US15417092

申请日：2017-01-26

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Beom Jun KIM ,  Seong Yeol SYN ,  Bong-Jun LEE ,  You Mee HYUN

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G09G3/2092 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G11C19/28

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.