Abstract:
An organic fight-emitting display device comprises a first thin-film transistor disposed on a substrate; and a second thin-film transistor disposed on the substrate and spaced apart from the first thin-film transistor. The first thin-film transistor comprises a first semiconductor layer, a first conductive layer disposed on the first semiconductor layer and that overlaps the first semiconductor layer, and a first insulating layer disposed between the first semiconductor layer and the first conductive layer. The second thin-film transistor comprises a second semiconductor layer, and a second conductive layer disposed on the second semiconductor layer and that overlaps the second semiconductor layer. The first semiconductor layer is disposed on a layer higher than the second semiconductor layer, the first semiconductor layer comprises an oxide semiconductor, the second semiconductor layer comprises low temperature polycrystalline silicon (LTPS), and the first insulating layer covers the entire first semiconductor layer.
Abstract:
The present disclosure relates to a display device, and the display device according to an embodiment includes: a substrate including a display area and a peripheral area; a plurality of light-emitting elements positioned in a display area; a plurality of pixel circuits connected to a plurality of light-emitting elements, respectively; a sensor positioned on the peripheral area of the substrate; a leakage current detecting circuit connected to the sensor; and a light emitting wiring connected to the leakage current detecting circuit and connected to at least one of the plurality of light-emitting elements, wherein the sensor includes a first sensor and the first sensor includes a first sensing transistor, and a first conductive pattern spaced apart from the channel of the first sensing transistor, and the first conductive pattern is positioned in the same layer as at least one of a plurality of layers configuring the transistor.
Abstract:
Provided is a display device comprising a display area including a plurality of pixels and a pad area disposed outside the display area, wherein the pad area includes a plurality of pads, and anchor structures positioned between two adjacent pads among the plurality of pads, the pad area includes a substrate, and at least one insulation layer that is positioned on the substrate and includes a first opening positioned between the two adjacent pads when viewed on the cross-section, and the anchor structure includes a first insulation layer that is positioned in the first opening, and does not overlap the pad.
Abstract:
A display panel includes: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels; a gate driver connected to the plurality of gate lines to apply a gate signal voltage; a data driver connected to the plurality of data lines to apply a data voltage and a negative data voltage; and a gate voltage divider for generating a gate signal voltage including gate-on and gate-off voltages to provided it to the gate driver. The gate voltage divider adjusts the gate-off voltage in accordance with a driving time of the display panel and a temperature of the display panel.
Abstract:
A display device includes a substrate, a first semiconductor layer on the substrate and including an oxide semiconductor, a first gate insulating film on the first semiconductor layer, a first conductive layer on the first gate insulating film, a first interlayer insulating film on the first conductive layer, and a second conductive layer on the first interlayer insulating film and connected to the first semiconductor layer through a through-hole. The through-hole includes a first through-hole passing through the first interlayer insulating film, and a second through-hole overlapping the first through-hole and passing through the first semiconductor layer. The second conductive layer is in contact with a side surface of the first semiconductor layer exposed at the second through-hole.
Abstract:
A gate driving circuit is provided. A gate driving circuit comprises a pull-up control unit including a control transistor, a pull-up unit, a carry unit which outputs a clock signal into a kth carry signal and a pull-down unit which pulls down a control node to an off voltage, wherein the control transistor includes one electrode and the other electrode connected to the control node, the one electrode and the other electrode being disposed on a gate electrode such that the one electrode and the other electrode being insulated from the gate electrode, wherein the gate electrode and the other electrode are disposed not to be overlapped with each other, and a distance between an upper surface of the gate electrode and a lower surface of the one electrode is longer than that of the upper surface of the gate electrode and a lower surface of the other electrode.
Abstract:
A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.