MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM

    公开(公告)号:US20240282378A1

    公开(公告)日:2024-08-22

    申请号:US18444848

    申请日:2024-02-19

    CPC classification number: G11C16/08 G11C16/0483

    Abstract: A memory system includes a memory device having a plurality of non-volatile memories, a buffer chip connected with each of the plurality of non-volatile memories, and a memory controller connected with the buffer chip and configured to provide a data strobe signal and a data signal to the buffer chip. The buffer chip includes a first loop coupled to a sampler circuit and configured to perform first monitoring on the data strobe signal and first duty correction on the data strobe signal based on the first monitoring, and a second loop coupled to a multiplexer and configured to, responsive to the first duty correction, perform second monitoring on the data strobe signal and second duty correction on the data strobe signal based on the second monitoring. The buffer chip is configured to store first and second duty correction information for at least one of the plurality of non-volatile memories.

    Reference voltage generator and semiconductor device including the same

    公开(公告)号:US10439632B2

    公开(公告)日:2019-10-08

    申请号:US16191367

    申请日:2018-11-14

    Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

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