SEMICONDUCTOR DEVICE
    11.
    发明申请

    公开(公告)号:US20240405014A1

    公开(公告)日:2024-12-05

    申请号:US18405843

    申请日:2024-01-05

    Abstract: The present disclosure relates to semiconductor devices. An example semiconductor device includes a first well region and a second well region isolated from each other by a first device isolation film; an NPN transistor provided by a first collector region formed in the first well region and including first conductivity-type impurities, and a first emitter region formed in the second well region and including the first conductivity-type impurities; a PNP transistor provided by a second emitter region formed in the first well region and including second conductivity-type impurities different from the first conductivity-type, and a second collector region formed in the second well region and including the second conductivity-type impurities; and an NMOS transistor including a source region and a drain region formed in the second well region and including the first conductivity-type impurities, and a gate structure disposed between the source region and the drain region.

    SEMICONDUCTOR DEVICE
    12.
    发明公开

    公开(公告)号:US20240259008A1

    公开(公告)日:2024-08-01

    申请号:US18236303

    申请日:2023-08-21

    CPC classification number: H03K17/08

    Abstract: A semiconductor device is provided. The semiconductor device includes: a first power pad; a second power pad; a signal pad; a clamping circuit connected between the first power pad and the second power pad; a driving circuit connected to the signal pad and including a pull-up circuit and a pull-down circuit; and a first gate-off circuit connected to the pull-down circuit. The first gate-off circuit is configured to connect a gate of the pull-down circuit and a source of the pull-down circuit to each other during an electrostatic discharge (ESD) event in which a high voltage is applied to the signal pad, and control a current generated by the high voltage to flow to the clamping circuit.

    SEMICONDUCTOR DEVICES WITH VOLTAGE ADJUSTMENT

    公开(公告)号:US20240136811A1

    公开(公告)日:2024-04-25

    申请号:US18350608

    申请日:2023-07-10

    CPC classification number: H02H9/04 H03K19/018571

    Abstract: A semiconductor device includes: a voltage clamping circuit including a plurality of first elements operating upon receiving a voltage having a first level and configured to output a clamp signal swinging in the first level by adjusting a voltage of an external input signal swinging in a second level more than twice the first level; a first buffer circuit configured to buffer the clamp signal; a level down shifter circuit configured to reduce the voltage of the clamp signal and output an internal input signal swinging in the first level between a predetermined reference voltage and a first power supply voltage higher than the reference voltage; and a second buffer circuit configured to buffer the internal input signal and transmits the internal input signal to a core circuit.

    Electrostatic discharge protection device

    公开(公告)号:US11908895B2

    公开(公告)日:2024-02-20

    申请号:US17542728

    申请日:2021-12-06

    CPC classification number: H01L29/0821 H01L29/735

    Abstract: An electrostatic discharge protection device includes: an emitter region disposed on a semiconductor substrate; a base region surrounding the emitter region; a first collector region surrounding the base region; a second collector region surrounding the first collector region; a second conductivity-type drift region below the emitter region, and being deeper than the base region; a second conductivity-type well region disposed below the base region, and having a junction interface with the second conductivity-type drift region; and a plurality of isolation portions disposed between the emitter region, the base region, and the first collector region and the second collector region.

    Electrostatic discharge protection element and semiconductor devices including the same

    公开(公告)号:US11817447B2

    公开(公告)日:2023-11-14

    申请号:US16986533

    申请日:2020-08-06

    CPC classification number: H01L27/0277 H01L27/0274 H01L27/0285

    Abstract: A semiconductor device includes a substrate including a P-well region, a gate electrode on the substrate, and a first region and a second region formed in the substrate on opposite sides adjacent to the gate electrode, the first region includes a first N-well region in the substrate and a second N-well region, a first impurity region, a second impurity region in the first N-well region, the second region includes a third impurity region in the substrate and a fourth impurity region in the third impurity region, a doping concentration of the second N-well region is greater than a doping concentration of the first N-well region, and a doping concentration of the second impurity region is greater than a doping concentration of the second N-well region.

    FinFET ESD device with fin-cut isolation region

    公开(公告)号:US11742342B2

    公开(公告)日:2023-08-29

    申请号:US17144354

    申请日:2021-01-08

    CPC classification number: H01L27/0255

    Abstract: An electrostatic discharge (ESD) device having a small size, a low turn-on voltage, and a low on resistance and an ESD protection circuit including the ESD device are provided. The ESD device includes a well formed in a substrate to have a first conductive type, an active region being defined at an upper portion of the substrate, a plurality of fins extending in a first direction to have a structure protruding from the substrate, a first conductive impurity region formed with first conductive impurities, a second conductive impurity region formed with second conductive impurities, and a fin-cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction to cut each fin, wherein a bottom surface of the fin-cut isolation region is higher than a bottom surface of the active region.

    ELECTROSTATIC DISCHARGE DEVICE AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT INCLUDING THE SAME

    公开(公告)号:US20210384188A1

    公开(公告)日:2021-12-09

    申请号:US17144354

    申请日:2021-01-08

    Abstract: An electrostatic discharge (ESD) device having a small size, a low turn-on voltage, and a low on resistance and an ESD protection circuit including the ESD device are provided. The ESD device includes a well formed in a substrate to have a first conductive type, an active region being defined at an upper portion of the substrate, a plurality of fins extending in a first direction to have a structure protruding from the substrate, a first conductive impurity region formed with first conductive impurities, a second conductive impurity region formed with second conductive impurities, and a fin-cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction to cut each fin, wherein a bottom surface of the fin-cut isolation region is higher than a bottom surface of the active region.

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