公开(公告)号：US20240222963A1

公开(公告)日：2024-07-04

申请号：US18402453

申请日：2024-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungil Do ,  Jinwoo Jung ,  Jooyoung Song ,  Mijin Lee ,  Chanhee Jeon

IPC: H02H9/04

CPC classification number: H02H9/045

Abstract: A device including a first clamp circuit connected between a first node and a second node, wherein the first clamp circuit includes: a symmetric bipolar transistor comprising a control terminal, a first current terminal and a second current terminal, wherein the first current terminal and the second current terminal are symmetrical to each other with respect to the control terminal; a first bipolar transistor electrically connected to the symmetric bipolar transistor and to the first node; and a second bipolar transistor electrically connected to the symmetric bipolar transistor and to the second node.

公开(公告)号：US20240235187A9

公开(公告)日：2024-07-11

申请号：US18350608

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eonguk Kim ,  Chanhee Jeon

IPC: H02H9/04 ,  H03K19/0185

CPC classification number: H02H9/04 ,  H03K19/018571

Abstract: A semiconductor device includes: a voltage clamping circuit including a plurality of first elements operating upon receiving a voltage having a first level and configured to output a clamp signal swinging in the first level by adjusting a voltage of an external input signal swinging in a second level more than twice the first level; a first buffer circuit configured to buffer the clamp signal; a level down shifter circuit configured to reduce the voltage of the clamp signal and output an internal input signal swinging in the first level between a predetermined reference voltage and a first power supply voltage higher than the reference voltage; and a second buffer circuit configured to buffer the internal input signal and transmits the internal input signal to a core circuit.

公开(公告)号：US20240137023A1

公开(公告)日：2024-04-25

申请号：US18350640

申请日：2023-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eonguk Kim ,  Jinsu Jeong ,  Chanhee Jeon

IPC: H03K19/0185 ,  H03K3/356

CPC classification number: H03K19/018571 ,  H03K3/356113

Abstract: A level shifter includes: an input circuit receiving an input signal swinging between a reference voltage and a first power supply voltage having a level higher than a level of the reference voltage; an output circuit outputting an output signal swinging between a second power supply voltage having a level higher than the level of the first power supply voltage and a third power supply voltage having a level higher than the level of the second power supply voltage; and a tolerant circuit connected between the input circuit and the output circuit, and configured to limit an output voltage of the input circuit to a range between the reference voltage and the second power supply voltage.

公开(公告)号：US20220231126A1

公开(公告)日：2022-07-21

申请号：US17542728

申请日：2021-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongkyu Song ,  Jaehyun Yoo ,  Jangkyu Choi ,  Jin Heo ,  Changsu Kim ,  Chanhee Jeon

IPC: H01L29/08 ,  H01L29/735

Abstract: An electrostatic discharge protection device includes: an emitter region disposed on a semiconductor substrate; a base region surrounding the emitter region; a first collector region surrounding the base region; a second collector region surrounding the first collector region; a second conductivity-type drift region below the emitter region, and being deeper than the base region; a second conductivity-type well region disposed below the base region, and having a junction interface with the second conductivity-type drift region; and a plurality of isolation portions disposed between the emitter region, the base region, and the first collector region and the second collector region.

公开(公告)号：US20240421149A1

公开(公告)日：2024-12-19

申请号：US18582871

申请日：2024-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Jung ,  Kyoungil Do ,  Jooyoung Song ,  Chanhee Jeon

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/74

Abstract: A semiconductor device includes a substrate doped with first conductivity-type impurities, a first well doped with second conductivity-type impurities different from the first conductivity-type impurities, first active regions in the first well, the first active regions being doped with the first conductivity-type impurities and connected to a first pad through a first interconnection, second active regions outside the first well, the second active regions being doped with the second conductivity-type impurities and connected to a second pad through a second interconnection, third active regions around the first active regions in the first well and doped with the second conductivity-type impurities, and fourth active regions around the second active regions outside the first well and doped with the first conductivity-type impurities, wherein at least one of the third active regions and at least one of the fourth active regions are electrically connected to each other through a third interconnection.

公开(公告)号：US20240235553A9

公开(公告)日：2024-07-11

申请号：US18350640

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eonguk Kim ,  Jinsu Jeong ,  Chanhee Jeon

IPC: H03K19/0185 ,  H03K3/356

CPC classification number: H03K19/018571 ,  H03K3/356113

Abstract: A level shifter includes: an input circuit receiving an input signal swinging between a reference voltage and a first power supply voltage having a level higher than a level of the reference voltage; an output circuit outputting an output signal swinging between a second power supply voltage having a level higher than the level of the first power supply voltage and a third power supply voltage having a level higher than the level of the second power supply voltage; and a tolerant circuit connected between the input circuit and the output circuit, and configured to limit an output voltage of the input circuit to a range between the reference voltage and the second power supply voltage.

公开(公告)号：US20240222357A1

公开(公告)日：2024-07-04

申请号：US18400792

申请日：2023-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungil DO ,  Jinwoo Jung ,  Jooyoung Song ,  Chanhee Jeon

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0248 ,  H01L29/7408 ,  H01L29/7412

Abstract: Provided is a device including a first clamp circuit electrically connected between a first node and a second node, and a second clamp circuit electrically connected between the second node and a third node, wherein the first clamp circuit includes a first silicon controlled rectifier (SCR) including a first region of a first conductivity type electrically connected to the first node, a second region of a second conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type electrically connected to the second node, and a first gate electrode disposed over a channel region including a junction of the second region and the third region between the first region and the fourth region.

公开(公告)号：US20240193339A1

公开(公告)日：2024-06-13

申请号：US18532496

申请日：2023-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jordan Timothy Davis ,  Woojin Seo ,  Chanhee Jeon

IPC: G06F30/392 ,  G06F30/327 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/327 ,  G06F30/394 ,  G06F2115/06

Abstract: In an example method of analyzing an electrostatic discharge (ESD) network, input data characterizing a semiconductor device is received. The semiconductor device includes an input/output (I/O) pad, an ESD protection circuit, and at least one functional circuit. A common resistance of the ESD protection circuit is calculated based on the input data and using a plurality of resistances and at least one predetermined equation. The plurality of resistances are associated with the I/O pad, the ESD protection circuit, and the at least one functional circuit. A network analysis is performed on the semiconductor device by excluding the common resistance.

公开(公告)号：US11508718B2

公开(公告)日：2022-11-22

申请号：US16921846

申请日：2020-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sukjin Kim ,  Mijin Lee ,  Namho Kim ,  Chanhee Jeon

IPC: H01L27/02 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A semiconductor device includes first well regions in a substrate and spaced apart from each other, a connection doped region between the first well regions, and a first interconnection line electrically connected to the connection doped region through a first contact. The first well regions and the connection doped region include impurities of a first conductivity type, and a concentration of the impurities in the connection doped region is higher than that in the first well regions. The first well regions extend into the substrate to a depth larger than that of the connection doped region. A first portion of the connection doped region is disposed in the first well regions and a second portion of the connection doped region contacts the substrate.

公开(公告)号：US20210175226A1

公开(公告)日：2021-06-10

申请号：US16986533

申请日：2020-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungjun Song ,  Hyunkwang Jeong ,  Changsu Kim ,  Chanhee Jeon

IPC: H01L27/02

Abstract: A semiconductor device includes a substrate including a P-well region, a gate electrode on the substrate, and a first region and a second region formed in the substrate on opposite sides adjacent to the gate electrode, the first region includes a first N-well region in the substrate and a second N-well region, a first impurity region, a second impurity region in the first N-well region, the second region includes a third impurity region in the substrate and a fourth impurity region in the third impurity region, a doping concentration of the second N-well region is greater than a doping concentration of the first N-well region, and a doping concentration of the second impurity region is greater than a doping concentration of the second N-well region.