公开(公告)号：US20160041791A1

公开(公告)日：2016-02-11

申请号：US14821663

申请日：2015-08-07

Applicant: Samsung Electronics Co., Ltd

Inventor： Chanyoung Hwang ,  Seungjin Yang

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0673 ,  G06F21/79

Abstract: An electronic device, an on-chip memory and a method of operating the on-chip memory are disclosed. The on-chip memory including an on-chip memory comprises: a plurality of design Intellectual Property (IPs), a memory that includes a storage area and a processor connected to the memory, wherein the processor is configured to monitor a memory traffic of at least one IP among the plurality of design IPs, and control usage of a storage area based on a result of the monitoring. According to the electronic device, the on-chip memory and the method of operating the on-chip memory of the present disclosure, in an AP-CP one chip structure, a stable communication is secured, memory latency is secured for a code required to process a real time of a CP, and in the AP-CP one chip structure, a communication bandwidth is improved.

Abstract translation: 公开了电子设备，片上存储器和操作片上存储器的方法。 包括片上存储器的片上存储器包括：多个设计知识产权（IP），包括存储区域的存储器和连接到存储器的处理器，其中处理器被配置为监视存储器的存储器业务量 所述多个设计IP中的至少一个IP，以及基于所述监视的结果来控制对存储区域的使用。 根据电子设备，片上存储器和本公开的片上存储器的操作方法，在AP-CP单芯片结构中，确保稳定的通信，保证存储器等待时间为 处理CP的实时，并且在AP-CP单芯片结构中，提高了通信带宽。

公开(公告)号：US11681904B2

公开(公告)日：2023-06-20

申请号：US16747989

申请日：2020-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongmin Tai ,  Insang Cho ,  Wonjae Lee ,  Chanyoung Hwang

IPC: G06N3/063 ,  G06F12/14

CPC classification number: G06N3/063 ,  G06F12/1458 ,  G06F2212/1052

Abstract: Disclosed in a processor chip configured to perform neural network processing. The processor chip includes a memory, a first processor configured to perform neural network processing on a data stored in the memory, a second processor and a third processor, and the second processor is configured to transmit a control signal to the first processor and the third processor to cause the first processor and the third processor to perform an operation.

公开(公告)号：US11574385B2

公开(公告)日：2023-02-07

申请号：US17364941

申请日：2021-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Insang Cho ,  Kiwon Yoo ,  Wonjae Lee ,  Daesung Cho ,  Chanyoung Hwang

IPC: G06T3/40 ,  G06F3/14 ,  G06N3/04 ,  G06N3/08

Abstract: Disclosed is an electronic apparatus. The electronic apparatus includes: a memory configured to store information regarding an artificial intelligence model including a plurality of layers; and a processor configured to perform interpolation processing on an input image and to process the interpolated image using the artificial intelligence model to obtain an output image, wherein the processor is configured to be operated in a first mode or a second mode based on an update of parameters used in at least one of the plurality of layers being required, the first mode including a mode in which the output image is obtained based on an image processed using the artificial intelligence model in which the parameters are updated and based on the interpolated image, and the second mode includes a mode in which the output image is obtained based on the interpolated image.

公开(公告)号：US20220027663A1

公开(公告)日：2022-01-27

申请号：US17494070

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongmin Tai ,  Insang Cho ,  Chanyoung Hwang

IPC: G06K9/62 ,  G06N3/04 ,  G06N3/08 ,  G06T3/40 ,  G06T7/00

Abstract: An electronic apparatus may include a memory that stores first information regarding a plurality of first artificial intelligence models trained to perform image processing differently from each other and second information regarding a second artificial intelligence model trained to identify a type of an image by predicting a processing result of the image by each of the plurality of first artificial intelligence models. The electronic apparatus may further include a processor configured to identify a type of an input image by inputting the input image to the second artificial intelligence model stored in the memory, and process the input image by inputting the input image to one of the plurality of first intelligence models stored in the memory based on the identified type.

公开(公告)号：US10579528B2

公开(公告)日：2020-03-03

申请号：US14957520

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanyoung Hwang ,  Seungjin Yang

IPC: C12N5/00 ,  G06F12/084 ,  G06F12/0842 ,  G06F1/32 ,  G06F12/0895 ,  G06F1/3234

Abstract: An electronic device and a method for controlling a sharable cache memory of the electronic device are provided. The electronic device includes a central processing unit including at least one core processor, at least one module, and a sharable cache memory including a controller, wherein the controller enables the sharable cache memory as a cache memory of the central processing unit if the central processing unit is in a working mode, and wherein the controller enables the sharable cache memory as a buffer of at least one of modules if at least one core processor of the central processing unit is transitioned to a sleep mode.