公开(公告)号：US10579528B2

公开(公告)日：2020-03-03

申请号：US14957520

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanyoung Hwang ,  Seungjin Yang

IPC: C12N5/00 ,  G06F12/084 ,  G06F12/0842 ,  G06F1/32 ,  G06F12/0895 ,  G06F1/3234

Abstract: An electronic device and a method for controlling a sharable cache memory of the electronic device are provided. The electronic device includes a central processing unit including at least one core processor, at least one module, and a sharable cache memory including a controller, wherein the controller enables the sharable cache memory as a cache memory of the central processing unit if the central processing unit is in a working mode, and wherein the controller enables the sharable cache memory as a buffer of at least one of modules if at least one core processor of the central processing unit is transitioned to a sleep mode.

公开(公告)号：US09684604B2

公开(公告)日：2017-06-20

申请号：US14792869

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjin Yang

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0895 ,  G06F12/0886

CPC classification number: G06F12/0895 ,  G06F12/0886 ,  G06F2212/401 ,  G06F2212/608

Abstract: An electronic device with a cache memory and a method of operating the electronic device are provided. The electronic device includes a cache memory including a plurality of cache lines each of which includes a first area with at least one storage space and a second area with at least one storage space, where the at least one storage space of the first area has a first size and the at least one storage space of the second area has a second size different from the first size, and a cache controller for storing the data requested for storage in one of the storage spaces of the first or second area, according to a compression factor associated with the data requested for storage when a request is made to store data in the cache memory.

公开(公告)号：US12254151B2

公开(公告)日：2025-03-18

申请号：US18507634

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyuk Lee ,  Hyunbin Park ,  Seungjin Yang ,  Jin Choi

IPC: G06F3/041 ,  G06F3/0488

Abstract: An electronic device is provided. The electronic device includes a touch sensor, a processor, and a memory. The processor may determine a touch input from a user as at least one of a force-touch input or a long-touch input, based on received touch data, determine whether a result of determining the touch data matches an intention of the user, store data that does not match the intention of the user as a result of determination among the touch data in the memory, and determine a type of an artificial intelligence (AI)-based pre-learning model to be used in the electronic device, based on touch input accuracy and the data that does not match the intention of the user.

公开(公告)号：US11874995B2

公开(公告)日：2024-01-16

申请号：US17899138

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyuk Lee ,  Hyunbin Park ,  Seungjin Yang ,  Jin Choi

IPC: G06F3/041 ,  G06N3/045

CPC classification number: G06F3/0418 ,  G06N3/045

Abstract: According to various embodiments, an electronic device includes a memory storing deep learning models for determining a force touch, a touchscreen, and a processor configured to identify a touch input of a user through the touchscreen, receive touch pixel data for frames having a time difference based on the touch input, and identify whether the touch input is a force touch based on the touch pixel data. The processor is configured to identify whether the touch input is the force touch using a first determination model among the deep learning models in response to identifying that the touch input is reinputted a designated first number of times or more within a designated time, and otherwise, identify whether the touch input is the force touch using a determination model having a lower computation load than the first determination model among the deep learning models.

公开(公告)号：US20160188244A1

公开(公告)日：2016-06-30

申请号：US14998160

申请日：2015-12-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjin Yang ,  Gilyoon Kim

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0679 ,  G06F3/0688

Abstract: A method of operating an electronic device includes storing access authority information indicating whether access to each of memory units of at least one access-restricted region from among a plurality of regions in a storage space is allowed or not. The method further includes, when an access request to the at least one access-restricted region is generated, determining whether to allow access based on the access authority information.

Abstract translation: 操作电子设备的方法包括存储指示是否允许对存储空间中的多个区域中的至少一个访问受限区域的每个存储单元的访问的访问权限信息。 该方法还包括当生成对至少一个访问受限区域的访问请求时，基于访问权限信息确定是否允许访问。

公开(公告)号：US20160154735A1

公开(公告)日：2016-06-02

申请号：US14957520

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanyoung Hwang ,  Seungjin Yang

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F1/32 ,  G06F1/3275 ,  G06F12/0842 ,  G06F12/0895 ,  G06F2212/1028 ,  G06F2212/20 ,  G06F2212/455 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: An electronic device and a method for controlling a sharable cache memory of the electronic device are provided. The electronic device includes a central processing unit including at least one core processor, at least one module, and a sharable cache memory including a controller, wherein the controller enables the sharable cache memory as a cache memory of the central processing unit if the central processing unit is in a working mode, and wherein the controller enables the sharable cache memory as a buffer of at least one of modules if at least one core processor of the central processing unit is transitioned to a sleep mode.

Abstract translation: 提供了一种用于控制电子设备的共享高速缓冲存储器的电子设备和方法。 电子设备包括中央处理单元，该中央处理单元包括至少一个核心处理器，至少一个模块和包括控制器的可共享高速缓存存储器，其中如果中央处理器将控制器作为中央处理单元的高速缓存存储器， 单元处于工作模式，并且其中如果中央处理单元的至少一个核心处理器转换到休眠模式，则控制器使得可共享高速缓冲存储器作为至少一个模块的缓冲器。

公开(公告)号：US20160041791A1

公开(公告)日：2016-02-11

申请号：US14821663

申请日：2015-08-07

Applicant: Samsung Electronics Co., Ltd

Inventor： Chanyoung Hwang ,  Seungjin Yang

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0673 ,  G06F21/79

Abstract: An electronic device, an on-chip memory and a method of operating the on-chip memory are disclosed. The on-chip memory including an on-chip memory comprises: a plurality of design Intellectual Property (IPs), a memory that includes a storage area and a processor connected to the memory, wherein the processor is configured to monitor a memory traffic of at least one IP among the plurality of design IPs, and control usage of a storage area based on a result of the monitoring. According to the electronic device, the on-chip memory and the method of operating the on-chip memory of the present disclosure, in an AP-CP one chip structure, a stable communication is secured, memory latency is secured for a code required to process a real time of a CP, and in the AP-CP one chip structure, a communication bandwidth is improved.

Abstract translation: 公开了电子设备，片上存储器和操作片上存储器的方法。 包括片上存储器的片上存储器包括：多个设计知识产权（IP），包括存储区域的存储器和连接到存储器的处理器，其中处理器被配置为监视存储器的存储器业务量 所述多个设计IP中的至少一个IP，以及基于所述监视的结果来控制对存储区域的使用。 根据电子设备，片上存储器和本公开的片上存储器的操作方法，在AP-CP单芯片结构中，确保稳定的通信，保证存储器等待时间为 处理CP的实时，并且在AP-CP单芯片结构中，提高了通信带宽。