公开(公告)号：US09455217B2

公开(公告)日：2016-09-27

申请号：US14528572

申请日：2014-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul Park ,  Hyeong-seob Kim ,  Kun-dae Yeom ,  Gwang-man Lim

IPC: H01L23/495 ,  H01L23/50 ,  H01L23/535 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49541 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/535 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01075 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48175 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.

Abstract translation: 提供了包括多个半导体芯片的半导体封装以及连接到半导体芯片的分离的引线组。 引线暴露于半导体封装的外部。 多个引线可以包括用于第一芯片组的第一引线组和用于第二芯片组的第二引线组。 第一和第二芯片组是封装的一部分。

公开(公告)号：US20150021761A1

公开(公告)日：2015-01-22

申请号：US14308958

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul Park

IPC: H01L23/498 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/522 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A multi-chip package may include a package substrate, a plurality of semiconductor chips stacked stepwise on the package substrate, a logic chip and a first conductive wire. The logic chip may include a conductive bump electrically connected to the package substrate. The first conductive wire may be electrically connected between the semiconductor chips and the logic chip.

Abstract translation: 多芯片封装可以包括封装衬底，在封装衬底上逐步堆叠的多个半导体芯片，逻辑芯片和第一导电线。 逻辑芯片可以包括电连接到封装衬底的导电凸块。 第一导线可以电连接在半导体芯片和逻辑芯片之间。

公开(公告)号：US08901750B2

公开(公告)日：2014-12-02

申请号：US14250934

申请日：2014-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul Park ,  Hyeong-seob Kim ,  Kun-dae Yeom ,  Gwang-man Lim

IPC: H01L23/02 ,  H01L23/535 ,  H01L23/495 ,  H01L23/50 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49541 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/535 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01075 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48175 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.