公开(公告)号：US11948872B2

公开(公告)日：2024-04-02

申请号：US17509224

申请日：2021-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Minjun Bae ,  Hyeonseok Lee ,  Gwangjae Jeon

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H01L23/34

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/18 ,  H01L23/34 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US11837551B2

公开(公告)日：2023-12-05

申请号：US17215517

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Seokhyun Lee ,  Gwangjae Jeon

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package includes a redistribution substrate having a semiconductor chip mounted on a top surface thereof with and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate includes a first redistribution pattern on a bottom surface of the connection terminal and comprising a first via and a first interconnection on the first via, a pad pattern between the first redistribution pattern and the connection terminal and comprising a pad via and a pad on the pad via, and a second redistribution pattern between the first redistribution pattern and the pad pattern and comprising a second via and a second interconnection on the second via with a recess region where a portion of a top surface of the second interconnection is recessed. A bottom surface of the recess region is located at a lower level than a topmost surface of the second interconnection.

公开(公告)号：US11646260B2

公开(公告)日：2023-05-09

申请号：US17206291

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Eungkyu Kim ,  Gwangjae Jeon

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/18 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/13016 ,  H01L2224/1355 ,  H01L2224/13541 ,  H01L2224/1607 ,  H01L2224/16013 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17055 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81345 ,  H01L2224/81815

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.

公开(公告)号：US11508649B2

公开(公告)日：2022-11-22

申请号：US17222912

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eungkyu Kim ,  Jongyoun Kim ,  Gwangjae Jeon

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package may include a substrate and a semiconductor chip on the substrate. The substrate may include an inner insulating layer, a redistribution layer in the inner insulating layer, an outer insulating layer on the inner insulating layer, a connection pad provided in the outer insulating layer and electrically connected to the redistribution layer, and a ground electrode in the outer insulating layer. A top surface of the connection pad may be exposed by a top surface of the outer insulating layer, and a level of the top surface of the connection pad may be lower than a level of the top surface of the outer insulating layer. A level of a bottom surface of the ground electrode may be higher than a level of a top surface of the redistribution layer, and the outer insulating layer covers a top surface of the ground electrode.

公开(公告)号：US11348864B2

公开(公告)日：2022-05-31

申请号：US16885546

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Gwangjae Jeon

IPC: H01L23/498

Abstract: Disclosed are redistribution substrates and semiconductor packages including the same. For example, a redistribution substrate including a dielectric pattern, and a first redistribution pattern in the dielectric pattern is provided. The first redistribution pattern may include: a first via part having a first via seed pattern and a first via conductive pattern on the first via seed pattern, and a first wiring part having a first wiring seed pattern and a first wiring conductive pattern, the first wiring part being disposed on the first via part and having a horizontal width that is different from a horizontal width of the first via part. Additionally, the first wiring seed pattern may cover a bottom surface and a sidewall surface of the first wiring conductive pattern, and the first via conductive pattern is directly connected to the first wiring conductive pattern.