公开(公告)号：US12205939B2

公开(公告)日：2025-01-21

申请号：US17501108

申请日：2021-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohwan Lee ,  Seokhyun Lee ,  Jeongho Lee

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package may include a first redistribution layer, a passive device disposed on a top surface of the first redistribution layer, a bridge structure disposed on the top surface of the first redistribution layer and laterally spaced apart from the passive device, a second redistribution layer disposed on and electrically connected to the passive device and the bridge structure, conductive structures disposed between the first redistribution layer and the second redistribution layer and laterally spaced apart from the passive device and the bridge structure, a first semiconductor chip mounted on a top surface of the second redistribution layer, and a second semiconductor chip mounted on the top surface of the second redistribution layer. The conductive structures may include a signal structure and a ground/power structure, which is laterally spaced apart from the signal structure and has a width larger than the signal structure.

公开(公告)号：US12040264B2

公开(公告)日：2024-07-16

申请号：US17508250

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Kyounglim Suk ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204

Abstract: A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

公开(公告)号：US11973028B2

公开(公告)日：2024-04-30

申请号：US18105945

申请日：2023-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun Kim ,  Seokhyun Lee ,  Minjun Bae

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/565 ,  H01L21/76819 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3128 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401

Abstract: A method is provided and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.

公开(公告)号：US11869835B2

公开(公告)日：2024-01-09

申请号：US17892215

申请日：2022-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Jongyoun Kim ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L21/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49816

Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.

公开(公告)号：US11705341B2

公开(公告)日：2023-07-18

申请号：US17741751

申请日：2022-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Gwangjae Jeon

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894

Abstract: Disclosed are redistribution substrates and semiconductor packages including the same. For example, a redistribution substrate including a dielectric pattern, and a first redistribution pattern in the dielectric pattern is provided. The first redistribution pattern may include: a first via part having a first via seed pattern and a first via conductive pattern on the first via seed pattern, and a first wiring part having a first wiring seed pattern and a first wiring conductive pattern, the first wiring part being disposed on the first via part and having a horizontal width that is different from a horizontal width of the first via part. Additionally, the first wiring seed pattern may cover a bottom surface and a sidewall surface of the first wiring conductive pattern, and the first via conductive pattern is directly connected to the first wiring conductive pattern.

公开(公告)号：US20220199880A1

公开(公告)日：2022-06-23

申请号：US17693704

申请日：2022-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dahye Kim ,  Seokhyun Lee ,  Jungho Park

IPC: H01L33/62 ,  H01L33/48 ,  H01L33/56

Abstract: A display module package includes a semiconductor chip, a wiring member disposed on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip, a light emitting device array disposed on the wiring member and including a plurality of light emitting devices disposed on one surface, wherein the wiring member is between the semiconductor chip and the light emitting device, and a molding member disposed on the wiring member, sealing part of the light emitting device array, and having an opening for exposing the plurality of light emitting devices.

公开(公告)号：US11282995B2

公开(公告)日：2022-03-22

申请号：US16860255

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dahye Kim ,  Seokhyun Lee ,  Jungho Park

IPC: H01L33/62 ,  H01L33/48 ,  H01L33/56 ,  H01L25/16 ,  H01L25/00 ,  H01L25/075 ,  H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L27/15

Abstract: A display module package includes a semiconductor chip, a wiring member disposed on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip, a light emitting device array disposed on the wiring member and including a plurality of light emitting devices disposed on one surface, wherein the wiring member is between the semiconductor chip and the light emitting device, and a molding member disposed on the wiring member, sealing part of the light emitting device array, and having an opening for exposing the plurality of light emitting devices.

公开(公告)号：US11056461B2

公开(公告)日：2021-07-06

申请号：US16748138

申请日：2020-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonho Jang ,  Gwangjae Jeon ,  Dongkyu Kim ,  Jungho Park ,  Seokhyun Lee

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78

Abstract: Provided is a method of manufacturing a semiconductor package including providing a carrier substrate, providing sacrificial layer on the carrier substrate, the sacrificial layer including a first sacrificial layer and a second sacrificial layer, providing a redistribution wiring layer on the sacrificial layer, providing a plurality of semiconductor chips on the redistribution wiring layer, providing a mold layer provided on the sacrificial layer, the redistribution wiring layer, and the plurality of semiconductor chips, detaching the first sacrificial layer from the second sacrificial layer, and dicing the second sacrificial layer, the redistribution wiring layer, and the mold layer, wherein a diameters of the first sacrificial layer and the second sacrificial layer are respectively less than a diameter of the carrier substrate, and a diameter of the mold layer is greater than the diameter of the redistribution wiring layer and less than the diameter of the first sacrificial layer.

公开(公告)号：US20210111128A1

公开(公告)日：2021-04-15

申请号：US17130505

申请日：2020-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNG LIM SUK ,  Seung-Kwan Ryu ,  Seokhyun Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

Abstract: A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.

公开(公告)号：US10685890B2

公开(公告)日：2020-06-16

申请号：US16279118

申请日：2019-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Seokhyun Lee

IPC: H01L21/66 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.