公开(公告)号：US11309002B2

公开(公告)日：2022-04-19

申请号：US17109567

申请日：2020-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hundae Choi ,  Garam Choi

IPC: G11C7/22 ,  H03L7/081 ,  H03L7/085 ,  G11C8/10 ,  G11C7/10

Abstract: A delay locked loop circuit and a semiconductor memory device are provided. The delay locked loop circuit includes a phase detection and delay control circuit configured to detect a phase difference between a first internally generated clock signal the feedback clock signal to generate a first phase difference detection signal in response to a first selection signal being activated, to detect a phase difference between a second internally generated clock signal and the feedback clock signal to generate a second phase difference detection signal in response to a second selection signal being activated, and to change a code value in response to the first phase difference detection signal or the second phase difference detection signal.

公开(公告)号：US11177814B2

公开(公告)日：2021-11-16

申请号：US16800038

申请日：2020-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwapyong Kim ,  Hundae Choi

IPC: H03L7/081 ,  G11C7/22 ,  G11C8/18 ,  H03L7/18 ,  G11C7/10 ,  H03L7/085 ,  G11C8/10

Abstract: A delay locked loop circuit including: a clock signal input buffer to buffer an input clock signal and generate a reference clock signal; a delay unit to delay the reference clock signal in response to a coarse and fine delay code and generate an internal clock signal; a clock signal delay replica unit to delay the internal clock signal and generate a feedback clock signal; a coarse delay control unit to receive the reference and feedback clock signals, detect a time period between a transition time point of the reference clock signal and a transition time point of the feedback clock signal occurring before the transition time point of the reference clock signal, and generate a coarse delay code; and a fine delay control unit to compare a phase of the reference clock signal and a phase of the feedback clock signal, and generate a fine delay code.

公开(公告)号：US11145355B2

公开(公告)日：2021-10-12

申请号：US16822164

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwapyong Kim ,  Hundae Choi ,  Junha Lee

IPC: G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  H03K19/00

Abstract: A memory device includes a calibration circuit having a pull-up code generator including a pull-up resistor block and generating a pull-up code, and a pull-down code generator including a replica pull-up resistor block and a pull-down resistor block and generating a pull-down code, and an off chip driver/on die termination circuit providing a termination resistance having a resistance value set by the calibration circuit in a data reception operation and outputting data at an output strength set by the calibration circuit in a data output operation. In a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.