公开(公告)号：US10177166B2

公开(公告)日：2019-01-08

申请号：US15409674

申请日：2017-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Hyun Kang ,  Hyun Lee ,  Min-Su Kim ,  Ji-Kyum Kim ,  Jong-Woo Kim

IPC: H01L27/118 ,  G06F17/50

Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.

公开(公告)号：US11057026B2

公开(公告)日：2021-07-06

申请号：US16831452

申请日：2020-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongkyu Ryu ,  Minsu Kim ,  Ahreum Kim ,  Daeseong Lee ,  Hyun Lee

IPC: H03K3/356 ,  H03K3/012 ,  H03K19/20

Abstract: A semi-dynamic flip-flop includes a semiconductor substrate, first through fourth power rails, and at least one clock gate line. The first through fourth power rails are disposed on the semiconductor substrate, extend in a first direction, and are arranged sequentially in a second direction substantially perpendicular to the first direction. The at least one clock gate line is disposed on the semiconductor substrate, and extends in the second direction to pass through at least two regions among a first region between the first power rail and the second power rail, a second region between the second power rail and the third power rail, and a third region between the third power rail and the fourth power rail. The at least one clock gate line receives an input clock signal.

公开(公告)号：US10566977B2

公开(公告)日：2020-02-18

申请号：US16259631

申请日：2019-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ah-Reum Kim ,  Hyun Lee ,  Min-su Kim

IPC: H03K3/356 ,  H03K19/0185 ,  H03K19/00 ,  H03K3/037 ,  H03K3/012

Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

公开(公告)号：US10353000B2

公开(公告)日：2019-07-16

申请号：US15479310

申请日：2017-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doo-Seok Yoon ,  Min-Su Kim ,  Chung-Hee Kim ,  Dae-Seong Lee ,  Hyun Lee ,  Matthew Berzins ,  James Lim

IPC: G01R31/3177 ,  H03K3/037 ,  G01R31/317

Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.

公开(公告)号：US10068878B2

公开(公告)日：2018-09-04

申请号：US15215583

申请日：2016-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-gyu Kim ,  Ji-sun Hong ,  Su-jung Hyung ,  Hyun-ki Kim ,  Hyun Lee

IPC: H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L25/10 ,  H01L23/31

Abstract: Provided are a printed circuit board (PCB) capable of blocking introduction of impurities during a molding process so as to reduce damage on a semiconductor package, a method of manufacturing the PCB, and a method of manufacturing a semiconductor package by using the PCB. An embodiment includes an apparatus comprising: a substrate body comprising an active area and a dummy area on an outer portion of the active area, the substrate body extending lengthwise in a first direction; a plurality of semiconductor units mounted on the active area; and a barrier formed on the dummy area, wherein the barrier extends in the first direction.