公开(公告)号：US20180083099A1

公开(公告)日：2018-03-22

申请号：US15628675

申请日：2017-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGMIN BAEK ,  VIETHA NGUYEN ,  WOOKYUNG YOU ,  Sangshin JANG ,  BYUNGHEE KIM ,  Kyu-Hee HAN

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/768

Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.

公开(公告)号：US20170278797A1

公开(公告)日：2017-09-28

申请号：US15618811

申请日：2017-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGHO RHA ,  JONGMIN BAEK ,  WOOKYUNG YOU ,  SANGHOON AHN ,  NAE-IN LEE

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L21/321 ,  H01L21/288 ,  H01L21/306 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/02178 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.