公开(公告)号：US20150380421A1

公开(公告)日：2015-12-31

申请号：US14848423

申请日：2015-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang SIM ,  Jinhyun SHIN ,  Jong-Min LEE

IPC: H01L27/115 ,  H01L21/764

CPC classification number: H01L27/11524 ,  H01L21/764 ,  H01L29/42324

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

Abstract translation: 提供一种半导体存储器件及其制造方法。 半导体存储器件可以包括半导体衬底，其具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，设置在第一区域上的栅电极以跨越有源区域， 存储图案，设置在所述栅电极和所述有源区之间，阻挡绝缘层，设置在所述栅电极和所述电荷存储图案之间并在所述第一沟槽上延伸以限定所述第一沟槽中的第一气隙，以及间隔开的绝缘图案 从第二沟槽的底表面到第二沟槽中限定第二气隙。

公开(公告)号：US20140179096A1

公开(公告)日：2014-06-26

申请号：US14192140

申请日：2014-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hwang SIM ,  Jae-Bok BAEK

IPC: H01L21/28

CPC classification number: H01L21/28 ,  H01L21/764 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/40114 ,  H01L29/7881

Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point.

Abstract translation: 半导体器件包括：衬底，包括第一区域和第二区域;栅极组，设置在衬底的第一区域中，栅极组包括多个单元栅极图案和至少一个选择栅极图案，第一栅极图案布置 在衬底的第二区域中，覆盖栅极组的顶表面和侧表面的组间隔件，具有第一拐点的组间隔件和覆盖第一栅极的顶表面和侧表面的第一图案间隔件 第一图案间隔物具有第二拐点。