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    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20150380421A1

    公开(公告)日：2015-12-31

    申请号：US14848423

    申请日：2015-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hwang SIM ,  Jinhyun SHIN ,  Jong-Min LEE

    IPC: H01L27/115 ,  H01L21/764

    CPC classification number: H01L27/11524 ,  H01L21/764 ,  H01L29/42324

    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

    Abstract translation: 提供一种半导体存储器件及其制造方法。 半导体存储器件可以包括半导体衬底，其具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，设置在第一区域上的栅电极以跨越有源区域， 存储图案，设置在所述栅电极和所述有源区之间，阻挡绝缘层，设置在所述栅电极和所述电荷存储图案之间并在所述第一沟槽上延伸以限定所述第一沟槽中的第一气隙，以及间隔开的绝缘图案 从第二沟槽的底表面到第二沟槽中限定第二气隙。

    CAPACITOR STRUCTURES, DECOUPLING STRUCTURES AND SEMICONDUCTOR DEVICES INCLUDING THE SAME
    4.
    发明申请
    CAPACITOR STRUCTURES, DECOUPLING STRUCTURES AND SEMICONDUCTOR DEVICES INCLUDING THE SAME 审中-公开

    公开(公告)号：US20200098854A1

    公开(公告)日：2020-03-26

    申请号：US16697484

    申请日：2019-11-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-Min LEE ,  Jongryul JUN ,  Eun A. KIM ,  Jung-Bum LIM

    IPC: H01L49/02 ,  H01L27/108 ,  H01L27/08

    Abstract: Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

    CAPACITOR STRUCTURES, DECOUPLING STRUCTURES AND SEMICONDUCTOR DEVICES INCLUDING THE SAME
    6.
    发明申请
    CAPACITOR STRUCTURES, DECOUPLING STRUCTURES AND SEMICONDUCTOR DEVICES INCLUDING THE SAME 审中-公开

    公开(公告)号：US20190172904A1

    公开(公告)日：2019-06-06

    申请号：US16268185

    申请日：2019-02-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-Min LEE ,  Jongryul JUN ,  Eun A KIM ,  Jung-Bum LIM

    IPC: H01L49/02 ,  H01L27/08 ,  H01L27/108

    Abstract: Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

    ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME
    7.
    发明申请
    ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20170155746A1

    公开(公告)日：2017-06-01

    申请号：US15287900

    申请日：2016-10-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hae-Jung YANG ,  Seung-Joo LEE ,  Kwang-Eun GO ,  Kang-Sik KIM ,  Jae-Hoon WOO ,  Jong-Min LEE

    IPC: H04M1/02 ,  H05K9/00 ,  H05K7/20

    CPC classification number: H04M1/026 ,  G06F1/1637 ,  G06F1/203 ,  H04M1/0266 ,  H04M1/0277 ,  H04M1/0279 ,  H05K7/20509 ,  H05K9/0007

    Abstract: A method for manufacturing an electronic device, according to the present disclosure, may include: detecting positions of one or more heat sources, which are disposed in a printed circuit board or in a display of the electronic device, or a path of the heat that is diffused from the heat sources; selecting a heat radiating structure to correspond to the positions of the heat sources or the diffusion path; selecting an adiabatic member or a heat radiating member, which is disposed based the selected heat radiating structure to block or radiate the heat transferred from the heat source; and forming the selected heat radiating structure or disposing the selected adiabatic member or heat radiating member on the periphery of the heat source or on the diffusion path. According to various embodiments of the disclosure, the heat radiation improvement can be maximized and/or improved by improving the structure of a heat radiation path of the electronic device and by selecting and disposing heat radiating members in appropriate positions.

    CAPACITOR STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    8.
    发明申请
    CAPACITOR STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
    电容器结构和半导体器件，包括它们

    公开(公告)号：US20160365409A1

    公开(公告)日：2016-12-15

    申请号：US15159809

    申请日：2016-05-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Min LEE ,  HYONGSOO KIM ,  JONGRYUL JUN

    IPC: H01L49/02

    CPC classification number: H01L28/90 ,  H01L27/10852

    Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

    Abstract translation: 电容器结构包括彼此水平间隔开的多个底部电极，覆盖底部电极的侧壁的支撑结构，围绕支撑结构的顶部电极和底部电极，以及插入支撑结构和顶部之间的电介质层 电极，以及顶部电极和每个底部电极之间。 支撑结构的最上表面位于比每个底部电极的最上表面更高的水平面上。

    SEMICONDUCTOR MEMORY DEVICE, METHOD FOR FABRICATING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, METHOD FOR FABRICATING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230114139A1

    公开(公告)日：2023-04-13

    申请号：US17900172

    申请日：2022-08-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong-Hoon SON ,  Joon Sung KIM ,  Suk Kang SUNG ,  Gil Sung LEE ,  Jong-Min LEE

    IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

    Abstract: A semiconductor memory device may include a cell substrate including a cell array region and an extension region, a first mold structure on the cell substrate, a second mold structure on the first mold structure, a channel structure passing through the first and second mold structures on the cell array region, and a cell contact structure passing through the first and second mold structures on the extension region. The first mold structure and the second mold structure respectively include first gate electrodes and second gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region. The cell contact structure includes a lower conductive pattern connected to one of the first gate electrodes, an upper conductive pattern connected to one of the second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.

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