公开(公告)号：US20140264529A1

公开(公告)日：2014-09-18

申请号：US14290234

申请日：2014-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hwang SIM

IPC: H01L29/788

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11529 ,  H01L27/228 ,  H01L29/7881 ,  H01L29/792 ,  H01L43/02

Abstract: A semiconductor memory device includes a substrate including a cell region and a peripheral region, word lines on the substrate of the cell region, each of the word lines including a charge storing part and a control gate electrode sequentially stacked, and a peripheral gate pattern on the substrate of the peripheral region. Each of the control gate electrode and the peripheral gate pattern includes a high-carbon semiconductor pattern and a low-carbon semiconductor pattern, the low-carbon semiconductor pattern being on the high-carbon semiconductor pattern.

Abstract translation: 半导体存储器件包括：包括单元区域和外围区域的衬底，单元区域的衬底上的字线，每个字线包括依次堆叠的电荷存储部分和控制栅电极;以及周边栅极图案， 外围区域的基板。 控制栅电极和外围栅极图案中的每一个包括高碳半导体图案和低碳半导体图案，低碳半导体图案位于高碳半导体图案上。

公开(公告)号：US20130337643A1

公开(公告)日：2013-12-19

申请号：US13804398

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun SEONG ,  Jae-Hwang SIM

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28273 ,  H01L27/0629 ,  H01L27/11521 ,  H01L28/20 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a field trench defining an active region and a lower gate pattern on the active region, the lower gate pattern including a tunneling insulating pattern and a lower gate electrode pattern, filling a field insulating material in the field trench to form a field region, forming an upper gate pattern on the lower gate pattern, sequentially forming a stopping layer and a buffer layer on the field region and the upper gate pattern, forming a first resistive pattern on the buffer layer of the field region, and forming a second resistive pattern on the buffer layer on the upper gate pattern, forming an interlayer insulating layer covering the first and second resistive patterns, and performing a planarization process to remove a top surface of the interlayer insulating layer and to remove the second resistive pattern.

Abstract translation: 一种制造半导体器件的方法包括蚀刻衬底以形成在有源区上限定有源区和下栅极图案的场沟槽，下栅极图案包括隧道绝缘图案和下栅极电极图案，填充场绝缘 在沟槽中形成场区域，在下栅极图案上形成上栅极图案，在场区域和上栅极图案上依次形成停止层和缓冲层，在缓冲层上形成第一电阻图案 并且在上栅极图案上的缓冲层上形成第二电阻图案，形成覆盖第一和第二电阻图案的层间绝缘层，并执行平面化处理以去除层间绝缘层的顶表面，以及 以去除第二电阻图案。

公开(公告)号：US20130264649A1

公开(公告)日：2013-10-10

申请号：US13668883

申请日：2012-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hwang SIM

IPC: H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/823468 ,  H01L27/11521 ,  H01L29/66825

Abstract: A semiconductor device includes a substrate including an active region and a field region, first gate structures disposed on the active region, first air gaps disposed between the first gate structures, second gate structures disposed on the field region, second air gaps disposed between the second gate structures, and an interlayer insulating layer disposed on the first gate structures, the first air gaps, the second gate structures, and the second air gaps. A lowermost level of the second air gaps is lower than a lowermost level of the first gate structures.

Abstract translation: 半导体器件包括：衬底，其包括有源区和场区;布置在有源区上的第一栅极结构，设置在第一栅极结构之间的第一气隙，设置在场区上的第二栅极结构， 栅极结构和设置在第一栅极结构，第一气隙，第二栅极结构和第二气隙上的层间绝缘层。 第二气隙的最低水平低于第一门结构的最低水平。

公开(公告)号：US20130256778A1

公开(公告)日：2013-10-03

申请号：US13742557

申请日：2013-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hwang SIM

IPC: H01L29/788 ,  H01L43/02 ,  H01L29/792

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11529 ,  H01L27/228 ,  H01L29/7881 ,  H01L29/792 ,  H01L43/02

Abstract: A semiconductor memory device includes a substrate including a cell region and a peripheral region, word lines on the substrate of the cell region, each of the word lines including a charge storing part and a control gate electrode sequentially stacked, and a peripheral gate pattern on the substrate of the peripheral region. Each of the control gate electrode and the peripheral gate pattern includes a high-carbon semiconductor pattern and a low-carbon semiconductor pattern, the low-carbon semiconductor pattern being on the high-carbon semiconductor pattern.

Abstract translation: 半导体存储器件包括：包括单元区域和外围区域的衬底，单元区域的衬底上的字线，每个字线包括依次堆叠的电荷存储部分和控制栅电极;以及周边栅极图案， 外围区域的基板。 控制栅电极和外围栅极图案中的每一个包括高碳半导体图案和低碳半导体图案，低碳半导体图案位于高碳半导体图案上。

公开(公告)号：US20150325478A1

公开(公告)日：2015-11-12

申请号：US14665141

申请日：2015-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojun SEONG ,  Jae-Hwang SIM ,  Jeehoon HAN

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes stacking an etch target layer, a first mask layer, and a second mask layer on a first surface of a substrate. A plurality of first spacer lines are formed parallel to each other and a first spacer pad line on the second mask layer is formed. A third mask pad in contact with at least the first spacer pad line on the second mask layer is formed. The second mask layer and the first mask layer are etched to form one or more first mask lines, a first mask preliminary pad, and second mask patterns. Second spacer lines are respectively formed covering sidewalls of the first mask preliminary pad and the first mask lines. First mask pads are formed. The etch target layer is etched to form conductive lines and conductive pads connected to the conductive lines.

Abstract translation: 制造半导体器件的方法包括在衬底的第一表面上堆叠蚀刻目标层，第一掩模层和第二掩模层。 多个第一间隔线彼此平行地形成，并且形成第二掩模层上的第一间隔垫线。 形成与第二掩模层上的至少第一间隔垫线接触的第三掩模焊盘。 蚀刻第二掩模层和第一掩模层以形成一个或多个第一掩模线，第一掩模预焊垫和第二掩模图案。 分别形成覆盖第一掩模预备焊盘和第一掩模线的侧壁的第二间隔线。 形成第一掩模垫。 蚀刻目标层被蚀刻以形成连接到导线的导电线和导电焊盘。

公开(公告)号：US20130256761A1

公开(公告)日：2013-10-03

申请号：US13852578

申请日：2013-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hwang SIM

IPC: H01L27/02

CPC classification number: H01L27/0207 ,  H01L27/11519 ,  H01L27/11524

Abstract: A semiconductor device, and a method of fabrication the same, include selection gate patterns extending in a first direction on a substrate, cell gate patterns extending in parallel in the first direction between the selection gate patterns adjacent to each other, and contact pads connected to first end parts of the cell gate patterns, respectively. An insulating layer covers the selection gate patterns, the cell gate patterns, and the contact pads. The insulating layer includes a void or seam between the contact pads. A filling insulating layer fills the void or seam in the insulating layer.

Abstract translation: 半导体器件及其制造方法包括在衬底上沿第一方向延伸的选择栅极图案，在彼此相邻的选择栅极图案之间沿第一方向平行延伸的单元栅极图案以及连接到 分别是单元栅极图案的第一端部分。 绝缘层覆盖选择栅极图案，单元栅极图案和接触焊盘。 绝缘层包括接触垫之间的空隙或接缝。 填充绝缘层填充绝缘层中的空隙或接缝。

公开(公告)号：US20240130123A1

公开(公告)日：2024-04-18

申请号：US18208459

申请日：2023-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yejin PARK ,  Seung Yoon KIM ,  Heesuk KIM ,  Hyeongjin KIM ,  Sehee JANG ,  Minsoo SHIN ,  Seungjun SHIN ,  Sanghun CHUN ,  Jeehoon HAN ,  Jae-Hwang SIM ,  Jongseon AHN

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06541

Abstract: Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a first gate stack structure including a first dielectric pattern and a first conductive pattern that are alternately stacked with each other, a memory channel structure including a first memory portion that penetrates the first gate stack structure, a through contact including a first through portion at a level the same as a level of the first memory portion, and a connection contact including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion. A minimum width of the first memory portion is less than a minimum width of the first through portion and a minimum width of the first connection portion.

公开(公告)号：US20140061758A1

公开(公告)日：2014-03-06

申请号：US14072250

申请日：2013-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hwang SIM ,  Keon-Soo KIM ,  Kyung-Hoon MIN ,  Min-Sung SONG ,  Yeon-Wook JUNG

IPC: H01L29/788

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

Abstract translation: 在非易失性存储器件及其制造方法中，器件隔离图案和有源区域在衬底上沿第一方向延伸。 在基板的有源区上形成第一电介质图案。 导电堆叠结构布置在第一电介质图案上，并且在一对相邻的导电堆叠结构之间形成凹部。 保护层形成在堆叠结构的侧壁上，以保护堆叠结构的侧壁不沿着第一方向过度蚀刻。 保护层包括具有氧化物并设置在浮栅电极的侧壁上的防蚀层和控制栅极线的侧壁以及覆盖导电堆叠结构侧壁的间隔层。

公开(公告)号：US20140008712A1

公开(公告)日：2014-01-09

申请号：US14019698

申请日：2013-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hwang SIM

IPC: H01L29/788

CPC classification number: H01L29/788 ,  H01L21/76229 ,  H01L21/764

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.

Abstract translation: 一种制造半导体器件的方法包括形成彼此间隔开第一距离的多个串，每个串包括在第二预栅结构之间间隔第二距离小于第一距离的第一预栅极结构，形成第一绝缘层 覆盖第一和第二预选栅极结构，形成绝缘层结构以填充串之间的空间，形成牺牲层图案以部分地填充第一和第二预选栅结构之间的空间，去除未覆盖的第一绝缘层的一部分 通过所述牺牲层图案以形成第一绝缘层图案，使未被所述第一绝缘层图案覆盖的所述第一和第二预选栅极结构的部分与导电层反应以形成栅极结构，并且在所述栅极结构上形成覆盖层 在门结构之间形成气隙。

公开(公告)号：US20170221755A1

公开(公告)日：2017-08-03

申请号：US15398090

申请日：2017-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang SIM ,  Hojun SEONG ,  Bongtae PARK ,  Woo-Jung KIM

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L27/11529 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11573

Abstract: A semiconductor device may include a first conductive pattern having a line portion and a pad portion connected to the line portion on a substrate, a gate insulating pattern and a second conductive pattern sequentially stacked on the substrate, and a capping layer disposed on the first and second conductive patterns. A first trench is defined in an upper portion of the substrate adjacent to one side of the second conductive pattern, and the capping layer at least partially fills the first trench.