公开(公告)号：US20180089116A1

公开(公告)日：2018-03-29

申请号：US15685586

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuntae PARK ,  Youngmin Lee ,  Sungho Seo ,  Hwaseok Oh ,  JinHyeok Choi

IPC: G06F13/28 ,  H04L29/08 ,  G06F11/30 ,  H04L12/40 ,  H04L12/403

Abstract: According to at least some example embodiments of the inventive concepts, an electronic device includes an embedded storage device that is, configured to connect to a removable storage device, and configured to directly communicate with the removable storage device, when connected to the removable storage device; and an application processor connected to directly communicate with the embedded storage device and not directly connected with the removable storage device, wherein, the embedded storage device is configured to, in response to a disable command received from the application processor, decrease an amount of power supplied to all or some of circuits included in the embedded storage device, and provide a bypass path that is configured to transfer a normal command and data from the application processor to the removable storage device, when the removable storage device is connected to the bypass path.

公开(公告)号：US11614866B2

公开(公告)日：2023-03-28

申请号：US17389834

申请日：2021-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin Cho ,  Sungyong Seo ,  Sun-Young Lim ,  Uksong Kang ,  Chankyung Kim ,  Duckhyun Chang ,  JinHyeok Choi

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G06F12/0868 ,  G06F12/0893 ,  G11C11/00 ,  G06F13/16 ,  G06F12/121

Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

公开(公告)号：US11106363B2

公开(公告)日：2021-08-31

申请号：US16414893

申请日：2019-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin Cho ,  Sungyong Seo ,  Sun-Young Lim ,  Uksong Kang ,  Chankyung Kim ,  Duckhyun Chang ,  JinHyeok Choi

IPC: G06F12/121 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G06F12/0868 ,  G06F12/0893 ,  G11C11/00 ,  G06F13/16

Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

公开(公告)号：US10453507B2

公开(公告)日：2019-10-22

申请号：US15685654

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongwoo Jeong ,  Hwaseok Oh ,  JinHyeok Choi

IPC: G11C7/22 ,  G11C7/10 ,  G11C16/08 ,  G11C16/32 ,  G11C29/02 ,  G11C8/12 ,  G11C29/50

Abstract: Disclosed is an electronic device which includes an application processor configured to generate a reference clock, a first storage device configured to receive the reference clock from the application processor through a clock input port, to output the reference clock to a clock output port, and to communicate with the application processor by using the reference clock, and a second storage device configured to receive the reference clock from the clock output port and use the reference clock for communication with the first storage device.

公开(公告)号：US10437498B2

公开(公告)日：2019-10-08

申请号：US15697900

申请日：2017-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo Noh ,  Hyuntae Park ,  Sungho Seo ,  Hwaseok Oh ,  Youngmin Lee ,  JinHyeok Choi

IPC: G06F3/00 ,  G06F3/06 ,  G06F13/42 ,  G06F11/07 ,  G11C5/04

Abstract: An electronic device includes an application processor; and a first storage device that is, connected to the application processor and directly communicates with the application processor, and connected to a second storage device such that the second storage device communicates with the application processor through the first storage device, wherein the first storage device includes a reset converter configured to generate a software reset signal in response to a hardware reset signal received from the application processor, and wherein the software reset signal resets the second storage device.

公开(公告)号：US10296261B2

公开(公告)日：2019-05-21

申请号：US15702035

申请日：2017-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngmin Lee ,  Sungho Seo ,  Hyuntae Park ,  Hwaseok Oh ,  JinHyeok Choi

IPC: G06F3/06

Abstract: An electronic device includes an embedded storage device and an application processor. The embedded storage device is connected to directly communicate with a removable storage device which processes a packet having a first characteristic. The embedded storage device processes a packet having a second characteristic. The application processor is connected to directly communicate with the embedded storage device, but not directly connected to the removable storage device. The application processor processes a packet having a third characteristic. The embedded storage device compensates at least one of the first characteristic or the second characteristic, such that at least one of a first packet of the first characteristic received from the removable storage device or a second packet of the second characteristic in the embedded storage device is provided to the application processor according to the third characteristic.