公开(公告)号：US20210390049A1

公开(公告)日：2021-12-16

申请号：US17157323

申请日：2021-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo Kim ,  Jinin So ,  Jong-Geon Lee ,  Yongsuk Kwon ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F12/0804 ,  G06F11/20 ,  G11C11/4096 ,  G11C11/4093

Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

公开(公告)号：US20240256185A1

公开(公告)日：2024-08-01

申请号：US18628917

申请日：2024-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eldho Mathew PATHIYAKKARA THOMBRA ,  Prashant Vishwanath Mahendrakar ,  Jin In So ,  Jong-Geon Lee

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method for operating a Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) for DIMM-to-DIMM communication is provided. The NMP DIMM includes one or more ports for communicative connection to other NMP DIMMs. The method includes parsing, by one NMP DIMM, a NMP command received from a processor of a host platform, identifying data dependencies on one or more other NMP DIMMs based on the parsing, establishing communication with the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, receiving data from the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, processing the NMP command using the data received from one of the one or more other NMP DIMMs and data present in the one NMP DIMM, and sending a NMP command completion notification to the processor of the host platform.

公开(公告)号：US20200335141A1

公开(公告)日：2020-10-22

申请号：US16731908

申请日：2019-12-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Geon Lee ,  KYUDONG LEE ,  JINSEONG YUN

IPC: G11C5/14 ,  G06F1/3225 ,  G06F1/3234 ,  G11C5/04

Abstract: A power management integrated circuit includes first pads, second pads, a third pad, and a fourth pad that are configured to be connected with an external device, a regulation block that receives first voltages from the first pads, converts the first voltages to second voltages, and outputs the second voltages to the second pads, a communication block that receives a command through the third pad and outputs an internal information request received together with the command responsive to the command, and a logic block that controls an operation of the regulation block, receives the internal information request from the communication block, and outputs internal state information to the fourth pad based on the internal information request.