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    Method and system for generating memory maps
    1.
    发明授权
    Method and system for generating memory maps 有权

    公开(公告)号：US12293081B2

    公开(公告)日：2025-05-06

    申请号：US18310741

    申请日：2023-05-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Raghu Vamsi Krishna Talanki ,  Archita Khare ,  Eldho P. Mathew ,  Jin In So ,  Jong-Geon Lee ,  Venkata Ravi Shankar Jonnalagadda ,  Vishnu Charan Thummala

    IPC: G06F3/06

    Abstract: The present disclosure relates to field of Dual In-Line Memory Modules that discloses method and system for generating memory maps. The method comprises detecting, by computing system, at least one of DIMM and one or more Dynamic Random Access Memory (DRAM) chips associated with computing system. The one or more accelerators are configured in at least one of DIMM and one or more DRAM chips. Further, the method includes determining accelerator information for each of one or more accelerators via at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of DIMM and one or more DRAM chips. Method includes generating unique memory map for each of one or more accelerators based on accelerator information of corresponding one or more accelerators. As a result, performance of computing system may be improved as accelerator capabilities of one or more accelerators are effectively utilized.

    Method and NMP DIMM for managing address map
    4.
    发明授权
    Method and NMP DIMM for managing address map 有权

    公开(公告)号：US11797440B2

    公开(公告)日：2023-10-24

    申请号：US17854772

    申请日：2022-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Raghu Vamsi Krishna Talanki ,  Eldho Pathiyakkara Thombra Mathew ,  Vishnu Charan Thummala ,  Vinod Kumar Srinivasan ,  Jin In So ,  Jong-Geon Lee

    IPC: G06F12/06

    CPC classification number: G06F12/063 ,  G06F2212/206

    Abstract: A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.

    Near memory processing dual in-line memory module and method for operating the same
    6.
    发明授权
    Near memory processing dual in-line memory module and method for operating the same 有权

    公开(公告)号：US11977780B2

    公开(公告)日：2024-05-07

    申请号：US17746562

    申请日：2022-05-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eldho Mathew Pathiyakkara Thombra ,  Prashant Vishwanath Mahendrakar ,  Jin In So ,  Jong-Geon Lee

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A method for operating a Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) for DIMM-to-DIMM communication is provided. The NMP DIMM includes one or more ports for communicative connection to other NMP DIMMs. The method includes parsing, by one NMP DIMM, a NMP command received from a processor of a host platform, identifying data dependencies on one or more other NMP DIMMs based on the parsing, establishing communication with the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, receiving data from the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, processing the NMP command using the data received from one of the one or more other NMP DIMMs and data present in the one NMP DIMM, and sending a NMP command completion notification to the processor of the host platform.

    METHOD AND NMP DIMM FOR MANAGING ADDRESS MAP
    7.
    发明申请
    METHOD AND NMP DIMM FOR MANAGING ADDRESS MAP 有权

    公开(公告)号：US20230004489A1

    公开(公告)日：2023-01-05

    申请号：US17854772

    申请日：2022-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Raghu Vamsi Krishna TALANKI ,  Eldho Pathiyakkara Thombra Mathew ,  Vishnu Charan Thummala ,  Vinod Kumar Srinivasan ,  Jin ln So ,  Jong-Geon Lee

    IPC: G06F12/06

    Abstract: A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.

    MEMORY SYSTEMS AND METHODS FOR OPERATING MEMORY SYSTEMS
    8.
    发明申请
    MEMORY SYSTEMS AND METHODS FOR OPERATING MEMORY SYSTEMS 有权

    公开(公告)号：US20250077433A1

    公开(公告)日：2025-03-06

    申请号：US18604783

    申请日：2024-03-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daehoon Kim ,  Hyungwon Park ,  Jin Jung ,  Minho Kim ,  Jin In So ,  Jong-Geon Lee ,  Hwanjun Lee ,  Minwoo Jang ,  Yeaji Jung

    IPC: G06F12/0862

    Abstract: Memory systems and methods for operating the same. A memory system comprises a first memory, a second memory having an operating speed different from that of the first memory, a storage unit configured to store an instruction, a prefetcher configured to update prefetcher data in response to occurrence of cache hits and a processor configured to execute the instruction stored in the storage unit. When the instruction is executed, the processor is configured to generate prefetcher friendly data by filtering the prefetcher data, set a prefetcher friendly bit in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory based on the prefetcher friendly data, and determine whether data of the first pointer area and the second pointer area are migrated, in consideration of a reference bit and the prefetcher friendly bit of the first and second pointer areas.

    Memory modules and methods of operating same
    10.
    发明授权
    Memory modules and methods of operating same 有权

    公开(公告)号：US11531618B2

    公开(公告)日：2022-12-20

    申请号：US17157323

    申请日：2021-01-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungsoo Kim ,  Jinin So ,  Jong-Geon Lee ,  Yongsuk Kwon ,  Jin Jung ,  Jeonghyeon Cho

    IPC: G06F12/0804 ,  G06F11/20 ,  G11C11/4093 ,  G11C11/4096 ,  H04N21/426

    Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

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